Design-Induced Latency Variation in Modern DRAM Chips
Design-Induced Latency Variation in Modern DRAM Chips
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DOI：
10.1145/3084464
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发表时间：
2017-06
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通讯作者：
Donghyuk Lee;S. Khan;Lavanya Subramanian;Saugata Ghose;Rachata Ausavarungnirun;Gennady Pekhimenko;Vivek Seshadri;O. Mutlu
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作者：
Donghyuk Lee;S. Khan;Lavanya Subramanian;Saugata Ghose;Rachata Ausavarungnirun;Gennady Pekhimenko;Vivek Seshadri;O. Mutlu
已经表明，在现代DRAM芯片内的单元之间存在变化。先前的工作已经研究和利用了几种形式的变化，如制造过程或温度引起的变化。我们凭经验证明了一种新的形式的变化，存在于一个真实的DRAM芯片内，引起的DRAM芯片中的不同组件的设计和放置：在DRAM中的不同区域，基于它们的相对距离从外围结构，需要不同的最小访问时间的可靠操作。特别是，我们表明，在大多数真实的DRAM芯片，细胞更接近的外围结构可以访问的速度比细胞更远。我们称这种现象为DRAM中的设计诱导变化。我们的目标是i）理解存在于真实的、最先进的DRAM芯片中的设计引起的变化，ii）利用它来开发低成本的机制，该机制可以动态地找到并使用最低的延迟来可靠地操作DRAM芯片，并且，因此，iii）在确保可靠的系统操作的同时提高整体系统性能。为此，我们首先通过实验证明和分析设计引起的变化，在现代DRAM设备的测试和表征96个DIBRATES（768 DRAM芯片）。我们的表征识别DRAM区域，容易出错，如果在较低的延迟操作，并发现其位置在给定的DRAM芯片代的一致性，由于设计引起的变化。基于我们广泛的实验分析，我们开发了两种机制，可靠地减少DRAM延迟。首先，DIVA分析使用运行时分析来动态地识别不引入故障的最低DRAM延迟。DIVA分析利用设计引起的变化，并定期分析脆弱的区域，以低成本确定最低的DRAM延迟。它是第一种动态确定可用于可靠操作DRAM的最低延迟的机制。DIVA Profiling在55°C时将读/写请求的延迟分别降低了35.1%/57.8%。我们的第二个机制，DIVA洗牌，洗牌数据，存储在脆弱的地区的值被映射到多个纠错码（ECC）码字。因此，DIVA Shuffling可以比传统ECC多纠正26%的多位错误。结合在一起，我们的两种机制将读/写延迟降低了40.0%/60.5%，这意味着在各种工作负载下，整体系统性能提高了14.7%/13.7%/13.8%（在2-/4-/8核系统中），同时确保了可靠的操作。
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip: different regions in DRAM, based on their relative distances from the peripheral structures, require different minimum access latencies for reliable operation. In particular, we show that in most real DRAM chips, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goals are to i) understand design-induced variation that exists in real, state-of-the-art DRAM chips, ii) exploit it to develop low-cost mechanisms that can dynamically find and use the lowest latency at which to operate a DRAM chip reliably, and, thus, iii) improve overall system performance while ensuring reliable system operation. To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our extensive experimental analysis, we develop two mechanisms that reliably reduce DRAM latency. First, DIVA Profiling uses runtime profiling to dynamically identify the lowest DRAM latency that does not introduce failures. DIVA Profiling exploits design-induced variation and periodically profiles only the vulnerable regions to determine the lowest DRAM latency at low cost. It is the first mechanism to dynamically determine the lowest latency that can be used to operate DRAM reliably. DIVA Profiling reduces the latency of read/write requests by 35.1%/57.8%, respectively, at 55°C. Our second mechanism, DIVA Shuffling, shuffles data such that values stored in vulnerable regions are mapped to multiple error-correcting code (ECC) codewords. As a result, DIVA Shuffling can correct 26% more multi-bit errors than conventional ECC. Combined together, our two mechanisms reduce read/write latency by 40.0%/60.5%, which translates to an overall system performance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core systems) across a variety of workloads, while ensuring reliable operation.