Characterisation of FPGA Clock Variability
Characterisation of FPGA Clock Variability
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FPGA 时钟可变性的表征
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
P. Cheung
中科院分区：
文献类型：
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作者：
N. P. Sedcole;Justin S. J. Wong;P. Cheung
随着集成电路按比例缩小，保持每个芯片的工艺参数的一致性变得困难。由此产生的性能变化需要新的设计策略来避免悲观的过度设计。量化了解不同电路元件对性能变化的贡献是此类策略的必要部分。本文提出了一种基于新颖的差分延迟测量电路来量化 FPGA 中时钟偏差变化的技术。该技术能够隔离时钟网络中不同组件对时钟偏差的影响。 65 nm FPGA 的结果表明，时钟偏差变化非常显着，其幅度与信号路径延迟变化相当。
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic over-design. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FPGAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65 nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.