Test application time reduction for sequential circuits with scan
Test application time reduction for sequential circuits with scan
复制标题
通过扫描减少时序电路的测试应用时间
DOI：
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发表时间：
1995
期刊：
影响因子：
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通讯作者：
K. Saluja
中科院分区：
文献类型：
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作者：
Soo Young Lee;K. Saluja
扫描设计缓解了时序电路的测试生成问题。然而，在测试应用阶段，扫描操作大大增加了测试时钟的总数。解决这一问题的经典方法是进行测试紧凑，获得的测试向量较少。在本文中，我们证明了这样的策略并不总是减少测试时钟或测试应用时间。我们的方法是在对具有全扫描或部分扫描的电路的测试生成期间，将扫描策略函数与每个测试向量相关联。本文提出了两种生成测试序列的算法，以减少应用测试序列所需的测试时钟数。该算法基于：(1)确定是否需要扫描操作的启发式算法；(2)通过选择合适的目标故障来控制顺序测试生成过程。在本文中，我们定义并研究了用于全扫描和部分扫描设计的不同扫描策略。我们提出了可用于在顺序测试生成过程中选择目标故障的近似度量。这些概念被集成到算法全扫描测试应用时间减少(TARF)和部分扫描测试应用时间减少(TARP)中。实现了算法，并将其用于一组ISCAS时序基准电路，验证了算法的有效性。实验表明，在全扫描设计中，与生成接近最佳测试集的COMPACTEST生成的向量相比，tArF生成的向量所需的测试时钟减少36%。同样，对于部分扫描设计，TARP实现了30%以上的累计测试时钟减少，而FAST的结果通常比其他ATPG系统产生的矢量更少。>；
Scan designs alleviate the test generation problem for sequential circuits. However, scan operations substantially increase the total number of test clocks during test application stage. Classical methods used to solve this problem perform test compaction and obtain fewer test vectors. In this paper we show that such a strategy does not always reduce the test clocks or test application time. Our approach is to associate a scan strategy function with each test vector during test generation for circuits with full or partial scan. The paper presents two algorithms to generate test sequences that reduce the number of test clocks required to apply the test sequences. The algorithms are based on: (1) heuristics that determine the need for scan operations; and (2) controlling sequential test generation process by choosing an appropriate target fault. In this paper we define and investigate different scan strategies for full and partial scan designs. We propose approximate measures that can be used for selection of a target fault during sequential test generation. These concepts are integrated into the algorithms Test Application time Reduction for Full scan (TARF) and Test Application time Reduction for Partial scan (TARP). The algorithms are implemented, and their efficiencies are demonstrated by using them for a set of ISCAS sequential benchmark circuits. The experiments show that, in full scan designs, TARF generated vectors require 36% fewer test clocks compared to the vectors from COMPACTEST that produces near optimal test sets. Similarly for partial scan designs, TARP achieves over 30% cumulative test clock reduction compared to the results from FASTEST which produced generally fewer vectors than other ATPG systems. >