Concurrent error detection in sequential circuits implemented using embedded memory of LUT-based FPGAs
Concurrent error detection in sequential circuits implemented using embedded memory of LUT-based FPGAs
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使用基于 LUT 的 FPGA 的嵌入式存储器实现时序电路中的并发错误检测
DOI：
10.1109/dft.2004.19
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
A. Krasniewski
中科院分区：
文献类型：
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作者：
A. Krasniewski
我们提出了一个并发错误检测（CED）计划的时序电路使用嵌入式存储器块和基于LUT的可编程逻辑块在FPGA中实现。所提出的方案被证明可以检测与导致电路的不正确状态或输出的电路的任何组件的单个输入或输出相关联的每个永久或瞬时故障。检测此类故障时没有延迟。实验结果表明，尽管所提出的CED方案的异构结构，开销是非常合理的。对于所检查的基准电路，占额外的EMB和额外的逻辑单元的组合开销在25.6%至61.0%的范围内，平均值为38.6%。
We propose a concurrent error detection (CED) scheme for a sequential circuit implemented using both embedded memory blocks and LUT-based programmable logic blocks available in FPGAs. The proposed scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in an incorrect state or output of the circuit. Such faults are detected with no latency. The experimental results show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very reasonable. For the examined benchmark circuits, the combined overhead, that accounts for both extra EMBs and extra logic cells, is in the range of 25.6% to 61.0%, with an average value of 38.6%.