Multibuffer delay line architectures for efficient contention resolution in optical switching nodes
Multibuffer delay line architectures for efficient contention resolution in optical switching nodes
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DOI：
10.1109/26.891219
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发表时间：
2000-12
期刊：
影响因子：
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通讯作者：
I. Chlamtac;A. Fumagalli;Changjin Suh
中科院分区：
文献类型：
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作者：
I. Chlamtac;A. Fumagalli;Changjin Suh
本文提出了一种高效的争用解决交换体系结构，可作为全光交换节点的基础。提出的解决方案建立在用作临时光存储和2/spl倍/2空间光子开关的光纤延迟线上，这种解决方案原理也称为Quadro或交换延迟线（SDLs）。sdl的效率从根本上与其存储容量有关，即光纤延迟线的长度，而其成本则取决于2/ sp1次/2光子开关的数量，即开关中的级数。这项工作提出了一种利用多缓冲光纤延迟线的解决方案，它允许多个数据包在每条线上同时存储（传播）。通过一种新颖的交换机控制，表明该解决方案增加了总存储容量，显著提高了交换机和网络性能，而不增加系统中2/ sp1倍/2交换机的数量，即成本。
This paper proposes an efficient contention resolution switching architecture which can serve as the basis for all-optical switching nodes. The presented solution builds on fiber delay lines used as temporary optical storage and 2/spl times/2 space photonic switches, a solution principle also known as Quadro or switched delay lines (SDLs). The efficiency of SDLs is fundamentally linked to its storage capacity, i.e., the length of the fiber delay lines, while its cost depends on the number of 2/spl times/2 photonic switches, i.e., the number of stages in the switch. This work presents a solution that makes use of multibuffer fiber delay lines which allow multiple packets to be concurrently stored (propagated) on each line. With a novel switch control, it is shown that this solution increases the total storage capacity and significantly improves switch and network performance, without increasing the number of the 2/spl times/2 switches in the system, i.e., its cost.