Transistor stuck-on fault detection tests for digital CMOS circuits
Transistor stuck-on fault detection tests for digital CMOS circuits
复制标题
数字 CMOS 电路的晶体管粘连故障检测测试
DOI：
10.1109/ets.2016.7519329
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
J. Rajski
中科院分区：
文献类型：
--
作者：
Xijiang Lin;S. Reddy;J. Rajski
通常，基于IDDQ测量的测试被用来检测数字CMOS电路中的晶体管粘连(TSON)故障。随着数字VLSI电路的最小特征尺寸的减小和VLSI芯片静态电流大小的增加，使用IDDQ测量来检测TSON故障变得困难(如果不是不可能的话)。因此，基于电压的测试，在这项工作中称为逻辑测试，正在被研究。在本文中，我们提出了一种基于门实现的布尔函数的逻辑测试生成方法。我们还表明，当可用时，这项工作中提出的测试应该比以前提出的基于IDDQ的测试更受欢迎。在ISCAS-和ITC‘99基准电路上的实验结果证明了所提逻辑测试的有效性。
Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.