Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics
Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics
复制标题
采用高 k 栅极电介质制造的 SRAM 随时间变化的 Vccmin 退化
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
C. Yu
中科院分区：
文献类型：
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作者：
J.C. Lin;A. Oates;C. Yu
本文给出了用高k栅压法制作的SRAM的电压感应Vccmin漂移的模拟结果。作者表明，基于高k的SRAM从根本上更容易受到Vccmin稳定性问题的影响，因为PMOS NBTI和NMOS PBTI导致位单元读取电压的附加降级。考虑到NBTI和PBTI现象的不同时间依赖性，与仅具有SiO2栅极电介质的器件的SRAM相比，Vccmin的漂移在早得多的时间增强。与SiO2相比，保持Vccmin稳定性对高k栅极MOSFET提出了更大的挑战
The paper presents the results of simulations of voltage-induced V ccmin drift of SRAMs fabricated with high-k gate dielectrics. The authors show that high-k based SRAMs are fundamentally more susceptible to Vccmin stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of Vccmin is enhanced at much earlier times compared to SRAMs that have SiO2 gate dielectric only devices. Maintaining Vccmin stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO2