Fast HBM Access with FPGAs: Analysis, Architectures, and Applications
Fast HBM Access with FPGAs: Analysis, Architectures, and Applications
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使用 FPGA 进行快速 HBM 访问：分析、架构和应用
DOI：
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发表时间：
2021
期刊：
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通讯作者：
M. Reichenbach
中科院分区：
文献类型：
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作者：
Philipp Holzinger;Daniel Reiser;Tobias Hahn;M. Reichenbach
在过去的几十年里，快速增长的计算能力和几乎停滞的内存带宽之间的差距不断恶化。最近，高带宽存储器（HBM）形式的3D芯片堆叠实现了多年来外部存储器吞吐量的首次重大飞跃。与传统DRAM相比，它用宽总线和大量独立通道来补偿其较低的时钟频率。然而，这也要求数据在所有通道上展开以达到全部吞吐量。以前的研究依赖于手动HBM数据划分方案，并将每个通道作为一个完全独立的实体处理。相反，本文还考虑了可扩展的硬件适应和方法系统设计的整体。在这个过程中，我们首先分析了Xilinx HBM FPGA上真实的世界测量的问题。然后，我们得出几个架构的变化，以提高吞吐量和简化加速器设计。最后，基于Roofline的模型，以更准确地估计预期的性能提前。通过这些措施，与Xilinx最先进的交换结构相比，我们能够将随机访问模式下的吞吐量提高3.78倍，将某些跨越式访问模式下的吞吐量提高40.6倍。
Over the past few decades, the gap between rapidly increasing computational power and almost stagnating memory bandwidth has steadily worsened. Recently, 3D die-stacking in form of High Bandwidth Memory (HBM) enabled the first major jump in external memory throughput in years. In contrast to traditional DRAM it compensates its lower clock frequency with wide busses and a high number of separate channels. However, this also requires data to be spread out over all channels to reach the full throughput. Previous research relied on manual HBM data partitioning schemes and handled each channel as an entirely independent entity. This paper in contrast also considers scalable hardware adaptions and approaches system design holistically. In this process we first analyze the problem with real world measurements on a Xilinx HBM FPGA. Then we derive several architectural changes to improve throughput and ease accelerator design. Finally, a Roofline based model to more accurately estimate the expected performance in advance is presented. With these measures we were able to increase the throughput by up to 3.78× with random and 40.6× with certain strided access patterns compared to Xilinx’ state-of-the-art switch fabric.