Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis
复制标题
用于基于布局的功率噪声侧通道泄漏分析的快速、全面的仿真方法
DOI：
10.1109/ises50453.2020.00038
复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Kazuki Monta
中科院分区：
文献类型：
--
作者：
Lang Lin;D. Selvakumaran;Deqi Zhu;N. Chang;C. Chow;M. Nagata;Kazuki Monta
侧通道攻击可以从硬件设备中提取大量“侧通道”测量的秘密信息，例如测量加密芯片的动态电压下降可以通过Power-Noise侧向通道披露秘密钥匙排放。要确定设计漏洞并验证针对侧向通道攻击的对策时间域模拟和所涉及的多物理模型。在本文中，我们提出了一种基于布局的功率噪声侧通道泄漏分析（SCLA）的快速，全面的模拟方法。通道发射模拟在时域中，一种新颖的直接向量控制（DVC）方法精确地应用于安全敏感的网络，以捕获所有侧渠道泄漏的源，我们还启用了一个依赖位置的scla root。潜在的布局设计弱点作为案例研究，我们验证了具有两个128位AES ASIC实现（基于CMOS的标准细胞逻辑和波动动态差异逻辑（WDDL））的测试芯片上提出的SCLA方法。两种模拟结果都在测量到透明（MTD）方面与硅测量结果相关，以证明我们的模拟框架准确检测了侧通道泄漏。
Side-channel attacks can non-invasively extract secret information from hardware devices with a large number of “side-channel” measurements. For example, measuring the dynamic voltage drop of a cryptographic chip can disclose the secret keys by power-noise side-channel emission. To identify the design vulnerabilities and to verify the design countermeasures against side-channel attacks, design time simulation tools are required. However, simulation of these power-noise side-channel emissions are highly complex and computationally intensive due to the scale of the time-domain simulation and the multi-physics models involved.In this paper, we have proposed a fast and comprehensive simulation methodology for the layout based power-noise Side-Channel Leakage Analysis (SCLA). To enable fast dynamic power-noise side-channel emission simulations in time domain, a novel Direct Vector Control (DVC) method is precisely applied to security-sensitive nets to capture all sources of side-channel leakage. Further, we have enabled a location dependent power-noise SCLA to root cause the potential layout design weakness. As a case study, we have validated the proposed SCLA methodology on a test chip which has two 128-bit AES ASIC implementations (CMOS based standard-cell logic and Wave Dynamic Differential Logic (WDDL)) embedded in it. Both Simulation results in terms of measurement-to-disclosure (MTD) have been correlated with silicon measurements to demonstrate the accurate detection of side-channel leakage by our simulation framework.
迈向集成电路和电子系统的安全组合：论 EDA 的作用
DOI：
10.23919/date48585.2020.9116483
发表时间：
2020
期刊：
Design Automation and Test in Europe (DATE 2020
影响因子：
--
作者：
Knechtel, Johann;Kavun, Elif Bilge;Regazzoni, Francesco;Heuser, Annelie;Chattopadhyay, Anupam;Mukhopadhyay, Debdeep;Dey, Soumyajit;Fei, Yunsi;Belenky, Yaacov;Levi, Itamar
通讯作者：
Levi, Itamar