A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation
A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation
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DOI：
10.1109/jssc.2019.2949255
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发表时间：
2020-05-01
影响因子：
5.4
通讯作者：
Buckwalter, James F.
中科院分区：
文献类型：
--
作者：
Ning, Kang;Fang, Yihao;Buckwalter, James F.
高峰值和平均效率是5G毫米波通信功率放大器（pa）的重要特征。本文回顾了CMOS技术中传统的共相方法所面临的挑战，并展示了一种低负载线阻抗的低损耗共相合成器。CMOS器件的不良特性的失相补偿与中和，单边化，和稳定网络的失相PA （OPA）。OPA在45纳米的CMOS绝缘体上硅（SOI）中实现，具有40%的6 db回退漏极效率（DE），同时提供17 dbm的峰值输出功率，峰值DE为50.5%。对于64-QAM，平均DE为31.3%，平均输出功率为0.1 dbm。OPA使用基于相位的查找表（LUT）证明64-QAM波形的误差矢量幅度（EVM）小于1.5%。使用16-QAM，比特率达到20gb /s， EVM为12%。据我们所知，这是高效PA的最高比特率。相邻通道漏比（ACLR）小于- 25dbc。
High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under -25 dBc.