A digital phase-locked loop with calibrated coarse and stochastic fine TDC
A digital phase-locked loop with calibrated coarse and stochastic fine TDC
复制标题
具有校准粗略和随机精细 TDC 的数字锁相环
DOI：
10.1109/jssc.2013.2259031
复制
发表时间：
2013
期刊：
影响因子：
--
通讯作者：
A. C. Carusone
中科院分区：
文献类型：
--
作者：
Amer Samarah;A. C. Carusone
粗细时间数字转换器 (TDC) 具有校准过程阶段和随后的随机精细阶段。上电时，使用基于代码密度测试的校准算法来最小化粗略 TDC 中的非线性。通过使用平衡平均方法，校准算法所需的寄存器数量减少了30%。根据粗略 TDC 结果，适当的时钟信号被复用为随机精细 TDC。 TDC 并入 0.13 μm CMOS 中的 1.9-2.54 GHz 数字锁相环 (DPLL)。 DPLL 总共消耗 15.2 mW，其中 TDC 消耗 4.4 mW。测量结果显示，带内相位噪声为 -107 dBc/Hz，相当于 4 ps TDC 分辨率，大约比该工艺技术中的逆变器延迟好一个数量级。集成随机抖动为 213 fs。校准可将最坏情况下的杂散降低 16 dB。
A coarse-fine time-to-digital converter (TDC) is presented with a calibrated course stage followed by a stochastic fine stage. On power-up, calibration algorithm based on a code density test is used to minimize nonlinearities in the coarse TDC. By using a balanced mean method, the number of registers required for calibration algorithm is a reduced by 30%. Based upon the coarse TDC resuls, the appropriate clock signals are multiplexed into a stochastic fine TDC. The TDC is incorporated into a 1.9-2.54 GHz digital phase locked loop (DPLL) in 0.13 μm CMOS. The DPLL consumes a total of 15.2 mW of which 4.4 mW are consumed in the TDC. Measurements show an in-band phase noise of -107 dBc/Hz which is equivalent to 4 ps TDC resolution, approximately an order of magnitude better than an inverter delay in this process technology. The integrated random jitter is 213 fs. The calibration reduces worst-case spurs by 16 dB.