Editorial: Special Section on CMP Architectures
Editorial: Special Section on CMP Architectures
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社论：CMP 架构特别章节
DOI：
10.1109/tpds.2007.70723
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
D. Tullsen
中科院分区：
文献类型：
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作者：
R. Iyer;D. Tullsen
当多个计算核心集成到同一芯片上时，就形成了 CHIP 多处理器 (CMP) 架构，形成单个强大的计算实体。几乎每个主要的高性能处理器制造商的芯片上都至少有两个内核（双核），并且他们的路线图越来越多核，这标志着大型单片单处理器的时代已经结束。这是因为越来越大的单处理器在功耗/性能、面积/性能或设计复杂性/性能方面无法很好地扩展。因此，这些处理器的持续性能扩展将主要集中在增加多线程吞吐量上。小型 CMP 平台的快速采用以及对高性能的追求不断加快处理器制造商考虑在芯片上添加更多内核的速度。在过去的十年中，学术界和工业界在客户端和服务器平台的 CMP 架构和设计方面的研究和开发取得了重大进展。而且，虽然我们已经成功进入 CMP 时代，但仍有一系列重大挑战和机遇有待深入研究。正在研究的一些广泛的研究领域包括 CMP 架构替代方案（用于核心、缓存、互连和内存）、CMP 设计和技术（工艺影响、3D 堆叠、电压/时钟域管理等新技术）、CMP 性能评估（新的模拟和建模技术、新兴应用程序和执行环境，如虚拟化）以及新颖的 CMP 架构和用例（非对称或异构架构、加速器等）。 CMP 架构还有许多问题有待解答。下面，我们列出了一些最引人注目的。
CHIP multiprocessor (CMP) architectures are formed when multiple compute cores are integrated onto the same chip, forming a single, powerful, computational entity. Nearly every major high-performance processor manufacturer has at least two cores (dual-core) on the die, and their roadmaps are increasingly multicore, signaling that the era of big, monolithic uniprocessors has ended. This results from the fact that ever-larger uniprocessors do not scale well in power/performance, area/performance, or design complexity/performance. Continued performance scaling of these processors will thus be focused primarily on increasing multithreaded throughput. The rapid adoption of small-scale CMP platforms and the quest for high performance continues to accelerate the rate at which processor manufacturers are considering adding more cores on the die. Over the last decade, there has been significant progress in research and development in both academia and industry on CMP architecture and design for client and server platforms. And, while we have successfully entered the era of CMP, there are a significant set of challenges and opportunities that are yet to be investigated deeply. Some of the broad research areas being investigated include CMP architecture alternatives (for core, cache, interconnect, and memory), CMP design and technologies (process implications, new technologies like 3D-stacking, voltage/clock domain management, etc.), CMP performance evaluation (new simulation and modeling techniques, emerging applications and execution environments like virtualization), and novel CMP architectures and use cases (asymmetric or heterogeneous architectures, accelerators, etc.). There are many questions that are still to be answered for CMP architectures. Below, we list a few of the most compelling ones.