Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks
Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks
复制标题
基于 16nm HK/MG 的替代 FPGA 逻辑块的工艺变化抗扰度
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
R. Demara
中科院分区：
文献类型：
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作者：
Ahmad Alzahrani;R. Demara
由于工艺变化（PV）的影响增加，半导体技术持续小型化到纳米尺度已经提高了高密度现场可编程门阵列（FPGA）器件的可靠性挑战。本文使用系统的自下而上的分析，通过确定PV对FPGA逻辑块的替代设计实现的相对影响来解决该问题。传统的设计结构的结果是通过详细的SPICE模拟和相关的结构风险功能。即，传输门（TG）和传输晶体管（PT）为基础的MUX架构实现查找表（LUT）进行了比较。在阈值电压变化σVth = 14%时，满足95%成品率目标的基于PT的设计可以表现出高达23.3%的延迟变化。如果考虑基于TG的LUT，PV影响可以降低到4.9%。最后，晶体管尺寸的影响进行了研究，作为一种方法，减轻PV敏感性的FPGA结构。
Continued miniaturization of semiconductor technology to nanoscale dimensions has elevated reliability challenges of high density Field-Programmable Gate Arrays (FPGA) devices due to increasing impacts of Process Variation (PV). The issue is addressed herein using a systematic bottom-up analysis by determining the relative influence of PV on alternate design realizations of FPGA logic blocks. Results for conventional design structures are obtained through detailed SPICE simulations and related to structural risk features. Namely, Transmission Gate (TG) and Pass Transistor (PT) based MUX architectures for realizing Look-Up-Tables (LUTs) are compared. At threshold voltage variation σVth = 14%, PT-based designs that meet the 95% yield objective can exhibit as high delay variation as 23.3%. PV impact can be reduced to 4.9% if TG-based LUT is considered. Finally, the impact of transistor sizing is investigated as a method of mitigating PV susceptibility in FPGA structures.