Fabrication and Simulation of 4H-SiC PiN Diodes Having Mesa Guard Ring Edge Termination
Fabrication and Simulation of 4H-SiC PiN Diodes Having Mesa Guard Ring Edge Termination
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DOI：
10.4028/www.scientific.net/msf.433-436.879
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发表时间：
2003-07
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影响因子：
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通讯作者：
I. Sankin;J. B. Dufrene;J. Merrett;J. Casady
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作者：
I. Sankin;J. B. Dufrene;J. Merrett;J. Casady
我们报告的设计，模拟和制作过程中的4 H-SiC的PiN二极管使用p型梅萨保护环（MGR）的边缘终端。所制备的二极管具有10 μ m的n型漂移区，掺杂浓度约为2 × 1016 cm-2，在0.5 μm的p+层中形成了MGR，有源受主浓度约为4 × 1018 cm-2。二极管在7.5 V正向压降和平均850 V击穿电压下探测到1 kA/cm的正向电流密度，而最好的器件表现出1100 V击穿。在相同的制造步骤期间使用SF6 ICP蚀刻限定器件活性区域和保护环两者。制造了宽度和间距为2 μm的MGR，其具有从4到20的不同数量的环。近年来，我们使用JTE结终端扩展（JTE Junction Termination Extension）制造了最好的高压SiC PiN二极管（例如，参见[1]）。尽管该技术具有出色的电性能，但其存在限制其实际实施的若干缺点。首先，JTE需要额外的注入，并且有时需要额外的注入后退火步骤。其次，为了最有效，JTE的有源浓度必须精确定制，以适应器件漂移区的掺杂分布。即使外延掺杂和JTE区中受主的激活百分比的微小变化也会引起器件阻断电压的显著变化。此外，快速高压脉冲可能会导致击穿电压不稳定，这是由于不完全的植入后激活和载流子冻结问题，这对于SiC中的p型杂质是典型的[2]。在这篇文章中，我们建议将梅萨保护环（MGR）作为SiC PiN二极管的一种有前途的边缘终止技术[3]。与传统的注入保护环相比，由于不需要昂贵的离子注入和注入后退火步骤，MGRs提供了一种低成本、低损伤的边缘终止的可能性。在下面的章节中，我们将讨论具有p型梅萨保护环边缘终端的PiN二极管的器件结构、模拟、制造工艺和实验结果，并与传统的离子注入保护环和JTE技术进行比较。a）B）图1：SF 6 ICP蚀刻后器件结构的SEM照片：4-环、0.01 mm 2器件（a）和15 K放大倍数下的MGR（B）的俯视图。433-436，pp 879-882 doi：10.4028/www.scientific.net/MSF.433-436.879 © 2003 Trans Tech Publications Ltd，Switzerland版权所有。未经Trans Tech Publications Ltd（www.scientific.net）的书面许可，不得以任何形式或任何方式复制或传播本文的任何内容。（Semanticscholar.org-12/03/20，10：57：06）制造从Cree Inc.为了模拟p +外延层，在650 ℃下以2.9x101cm 2的总剂量注入四能量Al盒轮廓。随后将样品在氩气中在1650 ° C下退火30分钟。使用[4]中发表的实验结果估计铝活化百分比约为4%。预期所得的0.5m p型层具有4 X 1018 cm 2的活性Al浓度。然后通过在SF6等离子体中蚀刻0.5 μ m的SiC来限定图1所示的器件结构。Ni背面欧姆接触在1050 ° C下退火2分钟，并且Ti p型阳极接触在850 ° C下使用2分钟退火形成。然后在阳极和阴极触点上蒸发一微米的银以降低接触电阻。MGR端接的PiN二极管的最终结构如图2a所示。未进行有意的表面钝化。除了具有MGR的器件之外，具有传统注入保护环的二极管（图2b）和具有JTE区域的二极管（图2c）也在同一晶片上制造。植入的保护环具有与MGR相同的植入时间表，并且JTE区域的植入剂量选择为2.2 × 10 13 cm 2。所有注入区的退火在同一步骤中进行。使用Keithley 237 SMU和Tektronix 576曲线描记器进行电流-电压测量。具有不同边缘终端的器件在7.5V下具有约1 kA/cm的均匀正向电流密度（图3a），同时显示出不同的阻断能力。特别地，具有MGR的二极管的反向击穿电压似乎通常小于具有传统边缘端接的器件的反向击穿电压。图二：所制造的二极管的示意性横截面：具有MGR的PiN二极管（a）、具有传统注入保护环的PiN二极管（B）以及具有JTE区域的PiN二极管（c）。
We report on the design, simulation and fabrication process of 4H-SiC PiN diodes using p-type mesa guard ring (MGR) edge termination. The fabri cated diodes had 10m ntype drift regions with doping of ~2x10 16 cm, and MGRs formed in 0.5 μm p+ layer with active acceptor concentration of approximately 4x10 18 cm. The diodes have probed forward current density of 1 kA/cm at 7.5 V forward drop and average 850 V breakdown voltages, while the best devices demonstrated 1100 V breakdowns. Both the device a ctive areas and guard rings were defined during the same fabrication step using a SF6 ICP etch. MGRs with a width and spacing of 2 μm were fabricated with a varying number o f rings ranging from 4 to 20. Introduction In recent years, the best reported high voltage SiC PiN diodes we re fabricated using JTE Junction Termination Extension (see for example, [1]). Despite the e xc ll nt electrical performance, this technique has several drawbacks which limit its pr actical implementation. First, JTE requires an additional implantation, and sometimes an addi tional post-implant annealing step. Second, to be most effective, JTE’s active concentra tion h s to be precisely tailored to fit the doping profile in the device drift region. Even small variation in the epi doping and the activation percentage of the acceptors in JTE region may cause significant changes in the device blocking voltage. In addition, fast high-voltage pulses may cause breakdown voltage instabilities due to incomplete post-implant activat ion nd carrier freezeout issues, typical for p-type impurities in SiC [2]. In this w ork we suggest the application of mesa guard rings (MGRs) as a promising edge termination tec h ique for SiC PiN diodes [3]. In comparison with traditional implanted guard rings, MGRs offer a potential for low-cost, lowdamage edge termination because expensive ion-implantation and post-implant anneal steps are unnecessary. In the following sections we discuss the device structure, simulation, fabrication process and experimental results of the PiN diodes having p-type mesa guard rings edge termination compared to traditional ionimplanted guard rings and JTE techniques. a) b) Figure 1: SEM picture of device structure after SF 6 ICP etch: top view of a 4-ring, 0.01 mm 2 device (a), and MGRs at 15 K magnification (b) Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 879-882 doi:10.4028/www.scientific.net/MSF.433-436.879 © 2003 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-12/03/20,10:57:06) Fabrication The n-type 4H-SiC wafer and 10m epi layer with n-type doping concentration of ~2x10 16 cm were bought from Cree Inc. In order to simulate a p + epi layer, a four-energy Al box profile was implanted with a total dose of 2.9x10 cm at 650oC. The sample was subsequently annealed for 30 min at 1650oC in argon. Aluminum activation percentage was estimated to be approximately 4% using experimental results published in [4]. The resulting 0.5m p-type layer was expected to have an active Al concentration of 4x10 18 cm. The device structures shown on Fig. 1 were then defined by etching 0.5 m of SiC in SF6 plasma. The Ni backside ohmic contact was annealed for 2 min at 1050oC, and the Ti ptype anode contact was formed using a 2-min anneal at 850 oC. One micron of silver was then evaporated on both the anode and cathode contacts to reduce contact resistance. The resulting structure of MGRs terminated PiN diode is shown on Fig. 2a. No intentional surface passivation was performed. In addition to the devices having MGRs, diodes with traditional implanted guard rings (Fig. 2b), and those having JTE regions (Fig. 2c) were fabricated on the same wafer. Implanted guard rings had the same i mplantation schedule as MGRs, and the implantation dose of the JTE region was chosen to be 2.2x10 13 cm. Annealing of all the implanted regions was performed in the same step. Experimental Results Current-voltage measurements were carried out using Keithley 237 SMU and a Tektronix 576 curve tracer. Devices with different edge terminations had a uniform forward current density of approximately 1kA/cm at 7.5V (Fig. 3a), while showing different blocking capabilities. In particular, reverse breakdown voltage of the diodes with MGRs appeared to be in general smaller than that of the devices having traditional edge termination. Figure 2: Schematic cross-sections of the fabricated diodes: PiN diode with MGRs (a), PiN diode with traditional implanted guard rings (b), and PiN diode with JTE region (c).