Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation
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DOI：
10.1145/871506.871549
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发表时间：
2003-08
期刊：
影响因子：
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通讯作者：
S. Mukhopadhyay;K. Roy
中科院分区：
文献类型：
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作者：
S. Mukhopadhyay;K. Roy
在本文中，我们已经开发了分析模型来估计的平均值和标准偏差的栅极，亚阈值，反向偏置源/漏结带-带隧穿（BTBT）和总泄漏在缩放的CMOS器件考虑变化的工艺参数，如设备的几何形状，掺杂分布，平带电压和电源电压。我们已经验证了该模型使用Monte Carlo模拟使用的NMOS器件的50 nm的有效长度和分析的结果，列举了不同的工艺参数对单个组件和总泄漏的影响。
In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.