A burst-mode word-serial address-event link-I transmitter design
A burst-mode word-serial address-event link-I transmitter design
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DOI：
10.1109/tcsi.2004.830703
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发表时间：
2004-07-01
影响因子：
5.1
通讯作者：
Boahen, KA
中科院分区：
文献类型：
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作者：
Boahen, KA
我们提出了一种用于可扩展多路访问芯片间链路的发射器，该发射器在深亚微米 CMOS 中制造的二维阵列之间进行二进制活动通信。传输由活动单元发起，但单元不是单独读取的。并行读取整行；这增加了通信容量和集成密度。访问是随机的，但并非不平等。在所有等待的行都得到服务之前，不会重新读取一行；随着更多的单元同时变得活跃，这会增加并行性。行和列地址标识活动单元，但它们不会同时传输。行地址后面依次跟随每个活动单元的列地址；这可以将焊盘数量减少一半，而不会牺牲容量。我们从高级描述开始，通过执行一系列程序分解来合成异步实现。使用这种设计的链路已在三代亚微米 CMOS 技术中成功实现。
We present a transmitter for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Transmission is initiated by active cells but cells are not read individually. An entire row is read in parallel; this increases communication capacity with integration density. Access is random but not inequitable. A row is not reread until all those waiting are serviced; this increases parallelism as more of its cells become active in the mean time. Row and column addresses identify active cells but they are not transmitted simultaneously. The row address is followed sequentially by a column address for each active cell; this cuts pad count in half without sacrificing capacity. We synthesized an asynchronous implementation by performing a series of program decompositions, starting from a high-level description. Links using this design have been implemented successfully in three generations of submicrometer CMOS technology.