High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels
High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels
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DOI：
10.1109/ispsd.2008.4538895
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发表时间：
2008-05
期刊：
影响因子：
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通讯作者：
M. Qiao;Bo Zhang;Zhiqiang Xiao;Jian Fang;Zhaoji Li
中科院分区：
文献类型：
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作者：
M. Qiao;Bo Zhang;Zhiqiang Xiao;Jian Fang;Zhaoji Li
提出了一种基于1 μ m厚硅层和2 μ m厚埋氧层的高压薄层SOI彩色等离子体显示器（PDP）驱动技术。具有厚栅极氧化物的高压pLDMOS、高压nLDMOS和低压CMOS与LOCOS隔离兼容。提出的技术包括两个方面：首先，场氧化层后注入（IFO）技术的发展，以实现浅结深的p场区，以避免pLDMOS的背栅（BG）效应引起的穿通击穿;第二，采用隔离氧化一致性工艺形成高压pLDMOS的厚栅氧化层、低压CMOS的场氧化层隔离同时实现了高压和低压CMOS之间的全介质隔离，而无需额外的掩模和工艺。与传统的结隔离或沟槽隔离技术相比，新的高压薄层SOI技术具有更好的工艺兼容性、更低的工艺复杂度和更低的寄生电容。采用该技术研制的PDP数据驱动芯片在电源电压为80 V、负载电容为50 pF时，输出级的上升和下降时间分别约为230 ns和160 ns。
A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology is developed for achieving shallow junction depth of p-field region to avoid punch-through breakdown induced by back-gate (BG) effect of pLDMOS; second, conforming technology of isolation and oxidation is adopted for forming thick gate oxide of high-voltage pLDMOS, field oxide isolation of low-voltage CMOS, and full dielectric isolation between high-voltage and low-voltage CMOS simultaneously without additional mask and process. Compared with conventional technology of junction or trench isolation, the new high-voltage thin layer SOI technology achieves better process compatibility with lower process complexity and lower parasitic capacitance. A PDP data driver IC using the developed technology shows that the rise and fall times of the output stages are about 230 ns and 160 ns respectively under the supply voltage of 80 V and load capacitance of 50 pF.