A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries
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DOI：
10.1109/acsd.2008.4574590
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发表时间：
2008-06
期刊：
影响因子：
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通讯作者：
Masashi Imai;T. Nanya
中科院分区：
文献类型：
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作者：
Masashi Imai;T. Nanya
本文提出了一种基于4选1编码方法的低功耗自定时组合电路和锁存器的设计方法。我们提出了一个1-out-4锁存电路，使用标准的单元库，以建立一个半定制的低功耗自定时的设计风格。所提出的电路的能量消耗是约18%，平均小于传统的双轨编码电路。
In this paper, we propose a design method for low-power self-timed combinational circuits and latches based on the 1-out-of-4 encoding method. We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded circuits.