All-wet fabrication process for ULSI interconnect technologies
All-wet fabrication process for ULSI interconnect technologies
复制标题
DOI：
10.1016/j.electacta.2005.04.069
复制
发表时间：
2005-11
影响因子：
6.6
通讯作者：
M. Yoshino;Yui Nonaka;J. Sasano;Itsuaki Matsuda;Y. Shacham-Diamand;T. Osaka
中科院分区：
文献类型：
--
作者：
M. Yoshino;Yui Nonaka;J. Sasano;Itsuaki Matsuda;Y. Shacham-Diamand;T. Osaka
“全湿法”是一种用于集成电路(IC)的新型超大规模集成电路(ULSI)互连技术。在PdCl2活化的自组装单分子膜(SAM)修饰的SiO_2/Si衬底上制备了化学镀NiB薄膜。该方法制备的NiB薄膜均匀，与衬底结合良好，具有良好的阻挡铜扩散的扩散阻挡特性。将铜直接电沉积在起种子层作用的化学镀镍膜上。这是在没有任何传统的通过物理气相沉积(PDV)形成的导电层或粘结层的情况下完成的。通过二次离子质谱仪(SIMS)和方块电阻测量，对化学镀NiB层在不同温度下的热稳定性进行了研究。结果表明，化学镀NiB膜阻止了铜的扩散，并在400℃下保温30min，保持了膜层的完整性。由于选择性地沉积在铜线表面的化学NiB膜也适用于盖层，因此同样的化学镀NiB工艺也适用于同样通过“湿法”形成的盖层。我们的结论是，所提出的工艺对于亚100 nm技术是非常有前途的，因为它提供了各种理想的特性：它具有良好的阶跃复盖率，同时表现出良好的势垒和种子层特性。
“All-wet process” for fabrication of Cu wiring on a silicon chip was proposed as a novel ultra-large scale integration (ULSI) interconnect technology for integrated circuits (ICs) applications. Electroless-NiB film was deposited on SiO2/Si substrate modified by self-assembled-monolayer (SAM) activated with PdCl2. The NiB film formed by this method has highly uniform, with good adhesion to the substrate and with good diffusion barrier characteristics against Cu diffusion. Cu was electrodeposited directly on the electroless NiB film that acted as a seed layer. This was done without any conventional conductive or adhesive layer that is conventionally formed by physical vapor deposition (PDV). The thermal stability of electroless NiB layer as a barrier preventing copper from diffusing into the SiO2/Si substrate was evaluated by secondary ion mass spectroscopy (SIMS) and sheet resistance measurement at several annealing temperatures. It was confirmed that the electroless NiB film blocked Cu diffusion and kept the layer integrity under annealing temperatures of up to 400°C for 30min. The same process of electroless NiB was used for the capping layer that was also formed by “wet process”, as the electroless NiB film deposited selectively onto a surface of Cu wiring was also applicable to a capping layer. We conclude that the proposed process is very promising for sub-100nm technologies as it offers a variety of desirable properties: it has good step coverage while showing good barrier and seed layer properties.