Systolic Architecture for Computational Fluid Dynamics on FPGAs
Systolic Architecture for Computational Fluid Dynamics on FPGAs
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DOI：
10.1109/fccm.2007.20
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发表时间：
2007-04
期刊：
影响因子：
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通讯作者：
K. Sano;Takanori Iizuka;Satoru Yamamoto
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文献类型：
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作者：
K. Sano;Takanori Iizuka;Satoru Yamamoto
本文根据收缩期结构介绍了基于FPGA的流量求解器。我们表明，采用中央差异方案的分数方法可以表示为收缩期算法，因此收缩期结构适用于对流求解器的专用处理器。我们已经设计了一个2D收缩期的单元格，每个细胞都有一个具有MAC（乘法和累积）单元和本地内存的微型数据路径，以存储必要的数据以进行计算流体动力学。使用Altera Stratix II FPGA，我们实施了96（= 12倍8）单元，以60 MHz运行。由于MAC单元具有单精度浮点数的加法器和乘数，因此总峰值性能为11.5（= 96Times6060 MHztimes2）Gflops。我们选择了基于分数方法的基准计算，将2D平方驱动的腔流作为基准计算。对于此计算，基于FPGA的处理器仅在60 MHz下运行的是7.14和6.41倍的计算速度比Pentium4处理器分别在3.2 GHz时和ITANIUM2分别为1.4 GHz。
This paper presents an FPGA-based flow solver based on the systolic architecture. We show that the fractional-step method employing central difference schemes can be expressed as a systolic algorithm, and therefore the systolic architecture is suitable for a dedicated processor to the flow solver. We have designed a 2D systolic array of cells, each of which has a micro-programmable data-path containing a MAC (multiplication and accumulation) unit and a local memory to store necessary data for computational fluid dynamics. With ALTERA Stratix II FPGA, we implemented 96(= 12 times 8) cells running at 60 MHz. Since the MAC unit has both an adder and a multiplier for single-precision floating-point numbers, the total peak performance is 11.5(= 96times60 MHztimes2) GFlops. We made a choice of 2D square driven cavity flow as a benchmark computation based on the fractional-step method. For this computation, the FPGA-based processor running only at 60 MHz achieved 7.14 and 6.41 times faster computations than Pentium4 processor at 3.2 GHz and Itanium2 at 1.4 GHz, respectively.