3D sequential integration opportunities and technology optimization
3D sequential integration opportunities and technology optimization
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3D 顺序集成机会和技术优化
DOI：
10.1109/iitc.2014.6831837
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
M. Vinet
中科院分区：
文献类型：
--
作者：
P. Batude;B. Sklénard;C. Fenouillet;B. Previtali;C. Tabone;O. Rozeau;O. Billoint;O. Turkyilmaz;H. Sarhan;S. Thuries;G. Cibrario;L. Brunet;F. Deprat;J.;F. Clermidy;M. Vinet
与基于TSV的3D IC相比，整体或顺序3D IC对垂直尺寸提出了“真实”的好处，因为堆叠层可以在晶体管尺度上连接到垂直层。与平面技术相比，单片3D可以实现大量的增益和性能总结了此概念的技术挑战：它提供了潜在解决方案的一般概述，以获得高性能低温顶晶体管，同时保持底部MOSFET完整性。
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.