Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew
复制标题
使用时间借用和非零时钟偏移的单相电平敏感电路的性能优化
DOI：
10.1145/589411.589437
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
I. Kourtev
中科院分区：
文献类型：
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作者：
B. Taskin;I. Kourtev
本文描述了一种用于具有电平敏感锁存器的大型同步电路性能优化的线性规划（LP）公式。提出的公式允许电路在更高的时钟频率下工作——即，通过应用非零时钟偏差调度[7]和时间借用[9]，具有更低的时钟周期。这种LP公式计算效率高，并证明了显着的电路性能改进。与[2]中记录的方法不同，这里提出的时钟周期最小化问题的LP模型是独立的，独立于所使用的特定LP求解器（求解算法）。引入改进的大M （MBM）方法，将电平敏感电路的非线性时序约束线性化为一组可解的全线性约束。时钟周期改进高达63%，证明了传统的基于触发器的电路具有零时钟偏差。使用工业线性求解器CPLEX[1]在ISCAS'89基准电路上显示了这些改进。
This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is stand-alone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1].