Silicon recess minimization during gate patterning using synchronous plasma pulsing
Silicon recess minimization during gate patterning using synchronous plasma pulsing
复制标题
使用同步等离子体脉冲在栅极图案化期间最小化硅凹槽
DOI：
10.1116/1.4737125
复制
发表时间：
2012
期刊：
影响因子：
--
通讯作者：
S. Banna
中科院分区：
文献类型：
--
作者：
C. Petit;E. Pargon;S. David;M. Darnon;L. Vallier;O. Joubert;S. Banna
With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.
