A 1300-V 0.34-$\Omega\cdot\hbox{cm}^{2}$ Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers
A 1300-V 0.34-$\Omega\cdot\hbox{cm}^{2}$ Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers
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DOI：
10.1109/ted.2010.2050100
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发表时间：
2010-06
影响因子：
3.1
通讯作者：
H. Elahipanah;A. Orouji
中科院分区：
文献类型：
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作者：
H. Elahipanah;A. Orouji
在本文中，首次提出了一种新型功率部分绝缘体上硅（PSOI）横向双扩散金属氧化物半导体（LDMOS）场效应晶体管，在源极和漏极附近具有双p和n电荷积累（CA）层（DCAL-PSOI）。所提出结构中的两个 p 和 n CA 层引入了两个新的高电场峰值。因此，由于位于p-和n-CA层以及掩埋氧化物表面中的电荷对漂移区中的电场进行调制，因此获得了更均匀的电场。因此，通过降低源极和漏极区域周围的高体电场，可以显着提高垂直击穿电压（BV）。分析了所提出的结构参数对器件特性的影响。对于漂移区长度为120μm的DCAL-PSOI LDMOS，仿真得到的最大BV为1317V，而在相同漂移区长度下，传统PSOI（C-PSOI）和传统绝缘体上硅（C-SOI）器件的最大BV分别为628和330V。此外，该器件表现出优异的比导通电阻（Ron，sp）为0.34 Ω·cm2，这表明优化后的DCAL-PSOI的导通电阻比C-PSOI降低了91%-95%。卓越的 BV 和 Ron, sp 产生 5.1 MW/cm2 的功率品质因数 (BV2/Ron, sp)。此外，Si窗口减轻了自热效应，并且与C-PSOI和C-SOI器件相比，所提出的结构的最高温度降低了。
In this paper, for the first time, a novel power partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor is proposed with dual p- and n- charge accumulation (CA) layers near the source and the drain (DCAL-PSOI). Two new high electric field peaks are introduced by the two p- and n- CA layers in the proposed structure. Hence, a more uniform electric field is obtained due to modulation of the electric field in the drift region by the charges located in the p- and n- CA layers and buried oxide surface. Therefore, the vertical breakdown voltage (BV) is significantly improved by reducing the high bulk electric field around the source and drain regions. The influences of the proposed structure parameters on device characteristics are analyzed. For the DCAL-PSOI LDMOS with a 120-μm drift region length, the maximum BV of 1317 V is obtained by the simulation, while at the same drift region length, the maximum BVs of the conventional PSOI (C-PSOI) and conventional silicon-on-insulator (C-SOI) devices are 628 and 330 V, respectively. Moreover, the device exhibits a superior specific on-resistance (Ron, sp) of 0.34 Ω·cm2, which shows that the on-resistance of the optimized DCAL-PSOI are decreased by 91%-95% in comparison to the C-PSOI. The superior BV and Ron, sp yield to a power figure of merit (BV2/Ron, sp) of 5.1 MW/cm2. Also, the Si window alleviates the self-heating effect, and the maximum temperature of the proposed structure reduces as compared with the C-PSOI and C-SOI devices.