Digital Enhanced V2-Type Constant On-Time Control Using Inductor Current Ramp Estimation for a Buck Converter With Low-ESR Capacitors
Digital Enhanced V2-Type Constant On-Time Control Using Inductor Current Ramp Estimation for a Buck Converter With Low-ESR Capacitors
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DOI：
10.1109/tpel.2012.2206403
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发表时间：
2013-03-01
影响因子：
6.7
通讯作者：
Mattavelli, Paolo
中科院分区：
文献类型：
--
作者：
Cheng, Kuang-Yao (Brian);Yu, Feng;Mattavelli, Paolo
提出了一种新的数字增强型V-2型恒定导通时间控制结构，用于解决降压变换器中使用低等效串联电阻（ESR）电容时的涟漪振荡问题。代替直接感测电感器电流，具有漂移补偿的电感器电流斜坡估计器被呈现为将虚拟ESR涟漪添加到输出电压。仅需要用模数转换器（ADC）对输入和输出电压进行采样，以估计电感器电流斜坡。由于ADC对电压检测的采样速率和分辨率要求通常不如直流检测严格，因此所提出的数字控制架构适用于低成本应用。此外，由于采样效应的极限环振荡也可以通过使用估计的电流斜坡得到改善。此外，所提出的数字增强V-2控制架构的小信号模型被提供来设计估计的电流斜坡幅度，以稳定系统并优化系统性能。文中还分析了漂移补偿的效果。所提出的控制架构与电流斜坡估计器的有效性已被验证的仿真和实验结果，通过使用基于FPGA的硬件平台。
This paper proposes a new digital enhanced V-2-type constant on-time control architecture for solving the ripple oscillation issues when using low-equivalent series resistance (ESR) capacitors in a buck converter. Instead of directly sensing the inductor current, an inductor current ramp estimator with the drift compensation is presented as adding a virtual ESR ripple to the output voltage. Only the input and output voltages are required to be sampled with analog-to-digital converters (ADCs) for estimating the inductor current ramp. Since the sampling rate and resolution requirements of ADCs for voltage sensing are usually less critical with compared to direct current sensing, the proposed digital control architecture is practical for low-cost applications. Besides, the limit-cycle oscillations due to the sampling effects can also be improved by using the estimated current ramp. Furthermore, the small-signal model of the proposed digital enhanced V-2 control architecture is provided to design the estimated current ramp amplitude to stabilize the system and to optimize the system performance. The drift compensation effect is also analyzed in this paper. The effectiveness of the proposed control architecture with the current ramp estimator has been verified with simulation and experimental results by using an FPGA-based hardware platform.