A high performance deblocking filter hardware for high efficiency video coding
A high performance deblocking filter hardware for high efficiency video coding
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DOI：
10.1109/tce.2013.6626260
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发表时间：
2013-10
影响因子：
4.3
通讯作者：
Erdem Ozcan;Yusuf Adibelli;Ilker Hamzaoglu
中科院分区：
文献类型：
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作者：
Erdem Ozcan;Yusuf Adibelli;Ilker Hamzaoglu
最近开发的高效视频编码（HEVC）国际视频压缩标准使用自适应去块滤波器来减少块伪影。去块滤波器提高主观和客观质量。但是，它们具有很高的计算复杂度。因此，在本文中，提出了文献中的第一个HEVC去块滤波器硬件。两个并行的数据通路中使用的建议的硬件，以提高其性能。该硬件是用Verilog HDL实现的。验证了Verilog RTL代码在FPGA板上正确工作。所提出的HEVC去块滤波器硬件可以每秒编码30个全HD（1920x1080）视频帧。因此，它可用于需要实时HEVC编码器或解码器的消费电子产品。
The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.