In-memory Multi-valued Associative Processor
In-memory Multi-valued Associative Processor
复制标题
内存中多值关联处理器
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
A. Eltawil
中科院分区：
文献类型：
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作者：
Mira Hout;M. Fouda;R. Kanj;A. Eltawil
内存关联处理器体系结构是克服内存墙瓶颈和实现向量/并行算术运算的一个很好的选择。在本文中，我们扩展的功能的关联处理器的多值算术。为了允许在内存中计算实现的算术或逻辑功能，我们提出了一种结构化的方法，使自动生成相应的查找表（LUT）。我们提出了两种方法来建立LUT：第一种方法，形式化的直觉背后的LUT通过排序和一个更优化的方法，减少了所需的写周期的数量。为了证明这些方法，我们提出了一种新的三进制关联处理器（TAP）的架构，用于实现高效的三进制向量就地加法。一个SPICE-MATLAB协同仿真器的实施，以测试TAP的功能，并评估所提出的AP三进制就地加法器实现的能量，延迟和面积方面的性能。结果表明，与二值AP加法器相比，三值AP加法器的功耗和面积分别降低了12.25%和6.2%。与最先进的三进制超前进位加法器相比，三进制AP还展示了52.64%的能量减少和高达9.5倍的延迟。
In-memory associative processor architectures are offered as a great candidate to overcome memory-wall bottleneck and to enable vector/parallel arithmetic operations. In this paper, we extend the functionality of the associative processor to multi-valued arithmetic. To allow for in-memory compute implementation of arithmetic or logic functions, we propose a structured methodology enabling the automatic generation of the corresponding look-up tables (LUTs). We propose two approaches to build the LUTs: a first approach that formalizes the intuition behind LUT pass ordering and a more optimized approach that reduces the number of required write cycles. To demonstrate these methodologies, we present a novel ternary associative processor (TAP) architecture that is employed to implement efficient ternary vector in-place addition. A SPICE-MATLAB co-simulator is implemented to test the functionality of the TAP and to evaluate the performance of the proposed AP ternary in-place adder implementations in terms of energy, delay, and area. Results show that compared to the binary AP adder, the ternary AP adder results in a 12.25\% and 6.2\% reduction in energy and area, respectively. The ternary AP also demonstrates a 52.64\% reduction in energy and a delay that is up to 9.5x smaller when compared to a state-of-art ternary carry-lookahead adder.