Flip chip assembly with sub-micron 3D re-alignment via solder surface tension

Flip chip assembly with sub-micron 3D re-alignment via solder surface tension
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通过焊料表面张力进行亚微米 3D 重新对准的倒装芯片组装

DOI:
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发表时间:
2015
期刊:
Electronic Components and Technology Conference
影响因子:
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通讯作者:
T. Barwicz
T. Barwicz
中科院分区:
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文献类型:
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作者:
J. Nah;Y. Martin;S. Kamlapurkar;S. Engelmann;R. Bruce;T. Barwicz

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我们通过实验演示了具有亚微米三维对准精度的倒装芯片组件。我们利用焊料表面张力将倒装芯片推入光刻定义的对准停止处。在回流期间,熔化焊料的表面张力可以使芯片移动一百多微米。我们使用这些运动通过将运动限制在光刻定义的机械挡块和芯片边缘对接来获得自对准。这种方法在 InP 激光器到 Si 光子组件中特别有用,其中需要亚微米对准以实现低光学连接损耗。在本报告中,我们的测试车辆包括硅光子芯片和硅制成的激光占位芯片。为了实现边缘发射单模激光器的自对准,需要很大的重新对准范围来克服+/- 15微米的激光切割公差和高吞吐量拾放工具的低+/- 10微米的放置精度。我们采用原位红外 (IR) 显微镜在焊接引起的重新对准过程中观察组装好的芯片。我们表明,芯片的自对准在焊料熔化的那一刻就开始了。横截面分析用于确认光刻停止点上的对准精度和接触。我们讨论与间隙高度和焊料体积相关的工艺窗口注意事项。
We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment accuracy. We employ solder surface tension to push the flipped chip into lithographically defined alignment stops. During reflow, surface tension forces of the melted solder can move a chip by more than a hundred microns. We use these motions to obtain self-alignment by constraining the motions to lithographically defined mechanical stops and chip edge butting. This approach is particularly useful in InP laser to Si photonic assemblies, where sub-micron alignment is required for low optical connection loss. In this report, our test vehicles comprise silicon photonic chips and laser placeholder chips made of silicon as well. To enable self-alignment of edge-emitting single-mode lasers, a significant re-alignment range is needed to overcome the laser cleaving tolerance of +/- 15 microns and the low +/- 10 microns placement accuracy of high-throughput pick-and-place tools. We employ in-situ infrared (IR) microscopy to look through the assembled chips during solder induced re-alignment. We show that the self-alignment of the chips starts at the moment the solders melt. Cross sectional analysis is used to confirm the alignment accuracy and contact on the lithographic stops. We discuss process window considerations related to standoff height and solder volume.