A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs
复制标题
一种具有复杂约束和差分对的统一印刷电路板布线算法
DOI：
10.1145/3394885.3431568
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Chung
中科院分区：
文献类型：
--
作者：
Ting;Devon J. Merrill;Yen;Chester Holtz;Chung
印刷电路板（PCB）布线问题近年来得到了广泛的研究。由于不断增长的净/引脚数、极高的引脚密度和独特的物理约束，PCB的手动布线已成为一项耗时的任务，以达到设计的最终目标。以前的工作分解成逃逸布线和区域布线问题，并分别关注这些问题。然而，这两个问题之间总是存在差距，需要大量的人力来来回微调算法。此外，以往的区域布线工作主要集中在逃逸布线球栅阵列（BGA）封装之间的布线。然而，在实践中，许多元件不是BGA封装的形式，例如无源器件、去耦电容和通孔引脚阵列。为了减轻以前的工作的不足之处，我们提出了一个全板布线算法，可以处理多个现实世界的复杂约束，以方便印刷电路板布线，并产生高质量的可制造布局。实验结果表明，该算法是有效的.具体来说，对于所有给定的测试用例，我们的路由器可以实现100%的可路由性，没有任何设计规则的违反，而其他两个国家的最先进的路由器无法完成路由的一些测试用例，并招致设计规则的违反。
The printed circuit board (PCB) routing problem has been studied extensively in recent years. Due to continually growing net/pin counts, extremely high pin density, and unique physical constraints, the manual routing of PCBs has become a time-consuming task to reach design closure. Previous works break down the problem into escape routing and area routing and focus on these problems separately. However, there is always a gap between these two problems requiring a massive amount of human efforts to fine-tune the algorithms back and forth. Besides, previous works of area routing mainly focus on routing between escaping routed ball-grid-array (BGA) packages. Nevertheless, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. To mitigate the deficiencies of previous works, we propose a full-board routing algorithm that can handle multiple real-world complicated constraints to facilitate the printed circuit board routing and produce high-quality manufacturable layouts. Experimental results show that our algorithm is effective and efficient. Specifically, for all given test cases, our router can achieve 100% routability without any design rule violation while the other two state-of-the-art routers fail to complete the routing for some test cases and incur design rule violations.