High-Performance H . 264 / AVC Intra Prediction Architecture for Ultra-HD Video Applications
High-Performance H . 264 / AVC Intra Prediction Architecture for Ultra-HD Video Applications
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通讯作者：
Gang He;Dajiang Zhou;Wei Fei;Zhixiang Chen;Jinjia Zhou;Satoshi Goto
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作者：
Gang He;Dajiang Zhou;Wei Fei;Zhixiang Chen;Jinjia Zhou;Satoshi Goto
1摘要-本文提出了一种用于超高清视频的H.264/AVC帧内预测设计。由于超高清对吞吐量的巨大要求，目前存在于较低分辨率的复杂性和数据依赖性等设计挑战变得更加关键。为了解决这些问题，我们首先提出了一种隔行块重排序方案和一种初步模式判决(PMD)策略来解决帧内模式判决和重建之间的数据依赖。同时，偏振模色散降低了硬件成本。针对流水线延迟较大的问题，提出了一种基于概率的重构方案。此外，采用硬件重用策略，包括共享精细决策模块和PE可重用预测生成器，以进一步优化设计。结果，硬件复杂度在面积和频率方面降低了77%，处理一个宏块(MB)平均需要33个周期。实现结果表明，在273 MHz的频率下，我们的设计可以支持高达7680x4320p 60fps的规格。该设计采用65nmCMOS451.5K门电路实现。
1 Abstract— This paper presents an H.264/AVC intra prediction design for ultra-high definition (ultra-HD) video. Due to the huge throughput requirements of ultra-HD, design challenges such as complexity and data dependency, which currently exist for lower resolutions, become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a preliminary mode decision (PMD) strategy to resolve the data dependency between intra mode decision and reconstruction. In the meantime, hardware cost is reduced by PMD. We also propose a probability-based reconstruction scheme to solve the problem of long pipeline latency. In addition, hardware reuse strategies, including a shared fine decision module and PE-reusable prediction generator, are applied to further optimize the design. As a result, the hardware complexity is reduced by 77% in terms of area and frequency, and it takes an average of 33 cycles to process a macroblock (MB). The implementation result demonstrates that our design can support up to the specification of 7680x4320p 60fps when running at 273MHz. The design is implemented with 451.5k gates in 65nm CMOS.