A high-performance reconfigurable computing solution for Peptide mass fingerprinting.
A high-performance reconfigurable computing solution for Peptide mass fingerprinting.
复制标题
用于肽质量指纹识别的高性能可重构计算解决方案。
DOI：
10.1007/978-1-60761-444-9_12
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Coca D
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文献类型：
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作者：
Coca D
高通量、基于MS的蛋白质组学研究正在产生非常大量的生物学相关数据。鉴于蛋白质组学在系统/合成生物学和生物标记物发现等新兴领域的核心作用，蛋白质组数据量预计将在未来几十年以前所未有的速度增长。目前，迫切需要高性能的计算解决方案来加速这些数据的分析和解释。特别是考虑到大型服务器场所需的巨大功耗、维护成本和占地面积，网格计算在这一领域取得的性能提升并不显著。本文介绍了一种基于现场可编程门阵列(现场可编程门阵列)的多肽海量指纹识别的高性能生物信息学解决方案。这种方法的核心是在定制的数字硬件上映射算法的概念，这些硬件可以编程在FPGA上运行。具体地说，在这种情况下，与肽质量指纹图谱相关联的整个计算流程，即原始质谱图处理和数据库搜索，已经被映射到定制硬件处理器上，所述定制硬件处理器被编程为在与传统PC服务器耦合的多FPGA系统上运行。与在3.06 GHz Xeon PC服务器上运行的软件实现算法的传统实现相比，该系统实现了近2000倍的速度。
High-throughput, MS-based proteomics studies are generating very large volumes of biologically relevant data. Given the central role of proteomics in emerging fields such as system/synthetic biology and biomarker discovery, the amount of proteomic data is expected to grow at unprecedented rates over the next decades. At the moment, there is pressing need for high-performance computational solutions to accelerate the analysis and interpretation of this data.Performance gains achieved by grid computing in this area are not spectacular, especially given the significant power consumption, maintenance costs and floor space required by large server farms.This paper introduces an alternative, cost-effective high-performance bioinformatics solution for peptide mass fingerprinting based on Field Programmable Gate Array (FPGA) devices. At the heart of this approach stands the concept of mapping algorithms on custom digital hardware that can be programmed to run on FPGA. Specifically in this case, the entire computational flow associated with peptide mass fingerprinting, namely raw mass spectra processing and database searching, has been mapped on custom hardware processors that are programmed to run on a multi-FPGA system coupled with a conventional PC server. The system achieves an almost 2,000-fold speed-up when compared with a conventional implementation of the algorithms in software running on a 3.06 GHz Xeon PC server.