Impact of Scaling Gate Insulator Thickness on the Performance of Carbon Nanotube Field Effect Transistors (CNTFETs)
Impact of Scaling Gate Insulator Thickness on the Performance of Carbon Nanotube Field Effect Transistors (CNTFETs)
复制标题
缩放栅极绝缘体厚度对碳纳米管场效应晶体管 (CNTFET) 性能的影响
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
R. Vaid
中科院分区：
文献类型：
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作者：
Devi Dass;R. Prasher;R. Vaid
由于按比例缩小Si MOSFET器件在短通道效应方面降低了器件性能。碳纳米管场效应晶体管（CNTFET）是一种克服MOSFET局限性的新型纳米电子器件。碳纳米管场效应晶体管（cntfet）被认为是下一代集成电路（IC）器件的有前途的候选者。为了探索cntfet在未来集成电路中的作用，评估其性能是很重要的。然而，要做到这一点，我们需要一个能够准确描述cntfet行为的模型，以便使用这些器件进行电路的设计和评估。在本文中，我们从转移特性、输出特性、平均速度、gm/Id比、移动电荷、量子电容/绝缘体电容、驱动电流（Ion）、离子/开关比、跨导和输出电导等方面研究了缩放栅绝缘体厚度对圆柱形弹道CNTFET器件性能的影响。我们得出的结论是，随着栅极绝缘体厚度的减少，器件指标如离子、离子/离合比、跨导和输出电导等都增加。此外，我们还得出结论，栅极绝缘子厚度的减小导致亚阈值斜率接近于60 mV/decade的理论极限，并且在室温下DIBL接近于零。
As scaling down Si MOSFET devices degrade device performance in terms of short channel effects. Carbon nanotube field effect transistor (CNTFET) is one of the novel nanoelectronics devices that overcome those MOSFET limitations. The carbon nanotube field effect transistors (CNTFETs) have been explored and proposed to be the promising candidate for the next generation of integrated circuit (IC) devices. To explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance. However, to do that we need a model that can accurately describe the behavior of the CNTFETs so that the design and evaluation of circuits using these devices can be made. In this paper, we have investigated the effect of scaling gate insulator thickness on the device performance of cylindrical shaped ballistic CNTFET in terms of transfer characteristics, output characteristics, average velocity, gm/Id ratio, mobile charge, quantum capacitance/insulator capacitance, drive current (Ion), Ion / Ioff ratio, transconductance, and output conductance. We concluded that the device metrics such as Ion, Ion / Ioff ratio, transconductance, and output conductance increases with the decrease in gate insulator thickness. Also, we concluded that the gate insulator thickness reduction causes subthreshold slope close to the theoretical limit of 60 mV/decade and DIBL close to zero at room temperature.