Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder
Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder
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DOI：
10.1109/tcsi.2020.3025847
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发表时间：
2021-01
期刊：
影响因子：
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通讯作者：
Zhenshan Xie;Xinmiao Zhang
中科院分区：
文献类型：
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作者：
Zhenshan Xie;Xinmiao Zhang
广义集成交织（GII）码嵌套里德-所罗门（RS）或BCH子码字以生成属于更强的RS或BCH码的码字。它们的超高速解码和良好的纠错能力使它们成为下一代太比特数字存储和通信的最佳候选者之一。嵌套解码阶段的关键方程求解器（KES）会造成时钟频率瓶颈，并占用GII解码器的很大一部分面积。最近的架构将关键路径减少到两个乘法器，并依靠减速技术的应用将其进一步减少到一个。减速技术需要两个子码字在嵌套的 KES 中交织。然而，大多数时候，嵌套译码只需要对一个子码字进行，就浪费了一半的时钟周期。本文提出了两种快速嵌套 KES 算法，这两种算法都在关键路径上有一个乘数，而不应用减速，从而将嵌套 KES 的延迟减少到近一半。短关键路径是通过算法重构来实现的，算法重构能够与多项式更新并行地预先计算标量。我们的第二个设计采用多项式的缩放版本来实现乘积项共享，以便每对处理元件中的乘法器数量从第一个设计中的 8 个减少到 4 个。开发了新颖的缩放和组合标量计算，以将关键路径保持为一个乘数。对于 $GF(2^{8})$ 上具有 3 个嵌套码字的 GII 代码示例，与之前的设计相比，我们的设计将嵌套 KES 所需的时钟周期数减少了 49.9%。此外，在相同的时序约束下，我们的第二个设计比第一个设计需要的面积减少了 22%。
Generalized integrated interleaved (GII) codes nest Reed-Solomon (RS) or BCH sub-codewords to generate codewords belonging to stronger RS or BCH codes. Their hyper-speed decoding and good error-correction capability make them one of the best candidates for next-generation terabit/s digital storage and communications. The key equation solver (KES) in the nested decoding stage causes clock frequency bottleneck and takes a large portion of the GII decoder area. Recent architectures reduce the critical path to two multipliers and rely on the application of the slow-down technique to further reduce it to one. The slow-down technique requires two sub-codewords to be interleaved in the nested KES. However, most of the time, the nested decoding only needs to be carried out on one sub-codeword and half of the clock cycles are wasted. This paper proposes two fast nested KES algorithms, both of which have one multiplier in the critical path without applying slow-down and accordingly reduce the latency of the nested KES to almost a half. The short critical path is achieved by algorithmic reformulations that enable the pre-computation of the scalars in parallel with polynomial updating. Our second design adopts scaled versions of the polynomials to enable product term sharing so that the number of multipliers in each pair of processing elements is reduced from 8 as in the first design to 4. Novel scaling and combined scalar computations are developed to keep the critical path one multiplier. For an example GII code over $GF(2^{8})$ that has 3 nested codewords, our designs achieve 49.9% reduction on the number of clock cycles needed in the nested KES compared to prior designs. Besides, our second design requires 22% less area than the first one under the same timing constraint.