Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices
Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices
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DOI：
10.1109/iedm.2010.5703332
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
K. Lim;Hyun-Yong Lee;Choongryul Ryu;K. Seo;U. Kwon;Seokhoon Kim;Jongwan Choi;Kyungseok Oh;
中科院分区：
文献类型：
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作者：
K. Lim;Hyun-Yong Lee;Choongryul Ryu;K. Seo;U. Kwon;Seokhoon Kim;Jongwan Choi;Kyungseok Oh;
提出了一种与高k/金属栅（HKMG）兼容的高性能源/漏（S/D）应力记忆（SMT）技术。采用掩模-刃位错模型可以模拟SMT产生的沟道应力，模拟结果与实际测量的沟道应力相吻合。SMT的极深预非晶化注入（派）在S/D区下产生了多个掩模边缘位错，使短沟道迁移率提高了40 ~ 60%。最后，超过10%的短沟道驱动电流增益实现了额外的S/D扩展优化。
High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.