An architecture of small-scaled neuro-hardware using probabilistically-coded pulse neurons
An architecture of small-scaled neuro-hardware using probabilistically-coded pulse neurons
复制标题
使用概率编码脉冲神经元的小型神经硬件架构
DOI：
10.1109/iecon.2000.973227
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
S. Okuma
中科院分区：
文献类型：
--
作者：
T. Kawashima;A. Ishiguro;S. Okuma
与传统方法相比，我们提出了一种可以在小型电路上实现的神经硬件架构。为了减小电路的规模，该架构采用了一种新的方法来计算膜电位和s型函数，通过将概率特性封装到两个脉冲之间的相对延迟中。所提出的架构使人们能够在最新的FPGA芯片上集成100多个神经元，这意味着与传统架构相比，小型化了13倍。
We present an architecture of a neuro-hardware that can be realized on a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and sigmoid function by encapsulating the probability properties into relative delay between two pulses. The proposed architecture enables one to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to the conventional architecture.