Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length
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双通道 CMOS 与 Si NFET 和应变 SiGe PFET 共同集成在具有低于 15 nm 栅极长度的纳米线器件架构中

DOI：
10.1109/iedm.2014.7047062
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发表时间：
2014
期刊：
2014 IEEE International Electron Devices Meeting
影响因子：
--
通讯作者：
M. Vinet
M. Vinet
中科院分区：
--
文献类型：
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作者：
P. Nguyen;S. Barraud;C. Tabone;L. Gaben;M. Cassé;F. Glowacki;J. Hartmann;M. Samson;V. Maffini;C. Vizioz;N. Bernier;C. Guedj;C. Mounet;O. Rozeau;A. Toffoli;F. Alain;D. Delprat;B. Nguyen;C. Mazure;O. Faynot;M. Vinet

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我们制作了具有应变SiGe沟道（cSiGe）p-FET和Si沟道n-FET的混合沟道Ω-栅CMOS纳米线（NW）。基于Ge富集技术的优化工艺流程导致与Si相比在长栅极长度下空穴迁移率增强+135%。cSiGe沟道的有效性也证明了超规模的p-FET纳米线（栅极长度LG=15纳米）与+90%离子电流的改善。
We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length LG=15 nm) with +90% ION current improvement.