Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption
Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption
复制标题
一种加速全同态加密的优化乘法结构
DOI：
10.1109/tc.2015.2498606
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发表时间：
2016-09
影响因子：
3.7
通讯作者：
Xiaolin Cao;C. Moore;Máire O’Neill;E. O'Sullivan;Neil Hanley
中科院分区：
文献类型：
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作者：
Xiaolin Cao;C. Moore;Máire O’Neill;E. O'Sullivan;Neil Hanley
大整数乘法是基于整数的全同态加密（FHE）方案的主要性能瓶颈。本文提出了两种优化的大整数乘法乘法器结构。第一个是整数fft乘法器的低延迟硬件架构。其次，利用低汉明权值（LHW）参数，在基于整数的FHE方案中创建了一种新的大整数乘法硬件架构。所提出的架构在Xilinx Virtex-7 FPGA平台上进行了实现、验证和比较。最后，利用所提出的实现来计算FHE加密步骤中整数上的大乘法。分析表明，与相应的原始基于整数的FHE软件实现相比，低延迟设计的速度提高系数高达26.2。当所提出的LHW架构与低延迟整数- fft加速器相结合来评估单个FHE加密操作时，性能结果表明速度可能提高约130倍。
Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.