FPGA Implementation of Metastability-Based True Random Number Generator
FPGA Implementation of Metastability-Based True Random Number Generator
复制标题
DOI：
10.1587/transinf.e95.d.426
复制
发表时间：
2012-02-01
影响因子：
0.7
通讯作者：
Ichiawa, Shuichi
中科院分区：
文献类型：
--
作者：
Hata, Hisashi;Ichiawa, Shuichi
真正的随机数生成器（TRNG）对于计算机安全性的基础很重要。尽管有一些由模拟电路组成的TRNG，但需要使用数字电路将TRNG应用于逻辑LSIS。一些数字trngs在自由运行的环振荡器中利用抖动作为熵的来源，可以消耗大量功率。另一种类型的TRNG利用了闩锁生成熵的稳定性。尽管这种TRNG主要是通过完整的LSI技术实施的，但本研究介绍了基于常见FPGA技术的实施。我们的Tang仅由逻辑门组成，并且可以以任何形式的逻辑LSI集成。我们的TRNG中的RS闩锁是用力实现的，可以通过最大程度地减少信号偏斜和内部节点的负载不平衡来确保随机性的质量。为了提高质量和吞吐量，Xored的输出为64-256。在Xilinx virtex-4 FPGA（XC4VFX20）上验证了派生的设计，并通过了NIST统计测试套件而无需进行后处理。我们的256个闩锁的TRNG占据了580片，同时达到12.5 Mbps的吞吐量。
True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TANG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.