On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices
On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices
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使用局部 STRASS 技术在先进 FDSOI CMOS 器件中获得高拉伸应变 Si 区域
DOI：
10.1002/pssc.201600028
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
M. Vinet
中科院分区：
文献类型：
--
作者：
A. Bonnevialle;S. Reboh;C. L. Royer;Y. Morand;J. Hartmann;D. Rouchon;J. Pedini;C. Tabone;N. Rambal;Anthony Payet;C. Plantier;F. Boeuf;M. Haond;A. Claverie;M. Vinet
应变增强器是提高先进CMOS FDSOI器件性能的有效途径。空穴迁移率在具有压缩沟道的pFET中更高。同时，对于具有拉伸沟道的nFET，电子迁移率更高。我们提出了一种替代技术，以毯覆sSOI衬底。“通过SOI上非晶化SiGe的顶部再结晶的应变硅”技术的效率先前已经在毯覆SOI上成功地证明（实现了+1.6GPa拉伸应变）。在这里，我们展示了一个简单而有效的STRASS模块集成在一个先进的FDSOI路线（14纳米的设计规则），它允许cointegrate拉伸硅nFET和不变的pFET。
在pFET已经被保护（SiN）之后，在SOI nFET图案中已经使用了STRASS技术。该工艺需要SiGe选择性外延、通过离子注入的掩埋非晶化、再结晶和SiGe去除。拉曼光谱用于表征相对于工艺条件（注入、有源区尺寸）的Si区域中的应力。此外，SiGe弛豫的机制将被讨论作为器件尺寸和SiGe层特性（厚度，Ge含量）的函数。我们证明了本地化的STRASS模块的成功整合：拉伸硅图案（nFET）与+1.6 GPa的应力水平，cointegrated与未修改的pFET。（© 2016 WILEY-VCH Verlag GmbH & Co. KGaA，魏因海姆）
Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the “Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI” technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs.
After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)