Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform
Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform
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DOI：
10.1109/tip.2015.2501725
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发表时间：
2021-12
影响因子：
10.6
通讯作者：
Cesar Carranza;D. Llamocca;M. Pattichis
中科院分区：
文献类型：
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作者：
Cesar Carranza;D. Llamocca;M. Pattichis
离散周期拉东变换（DPRT）已广泛用于涉及从投影重建图像的应用中。除了经典的应用之外，DPRT还可以用于计算快速卷积，避免使用与快速傅立叶变换相关的浮点运算。不幸的是，DPRT的使用受到需要计算大量加法和需要大量存储器访问的限制。本文介绍了一种快速和可扩展的方法，用于计算正向和反向DPRT，这是基于使用：一个并行阵列的定点加法器树;循环移位寄存器，以消除需要访问外部存储器组件时，选择输入数据的加法器树;一个图像块为基础的方法来计算DPRT，可以适应所提出的架构，以可用的资源;以及在一个或几个时钟周期中计算的快速转置，其不依赖于输入图像的大小。因此，对于一个N × N的图像（N素数），所提出的方法可以计算多达N2个加法每个时钟周期。与以前的方法相比，可扩展的方法提供了最快的已知实现不同的计算资源量。例如，对于一个251×251的图像，对于比脉动实现所需的触发器少大约25%的情况，我们可以将可扩展DPRT的计算速度提高36倍。对于最快的情况，我们引入优化的仅2N + log 2 N + 1和2N + 3 log 2 N + B + 2周期，这些架构可以分别计算DPRT及其逆，其中B是用于表示每个输入像素的位数。另一方面，可扩展DPRT方法需要比脉动实现更多的1-B加法，并且提供了速度和附加1-B加法之间的折衷。所有建议的DPRT架构实现在VHSIC硬件描述语言（VHDL）和验证使用现场可编程门阵列（FPGA）的实现。
The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: a parallel array of fixed-point adder trees; circular shift registers to remove the need for accessing external memory components when selecting the input data for the adder trees; an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the input image. As a result, for an N × N image (N prime), the proposed approach can compute up to N2 additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a 251×251 image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized just 2N + ⌈log2 N⌉ + 1 and 2N + 3 ⌈log2 N⌉ + B + 2 cycles, architectures that can compute the DPRT and its inverse in respectively, where B is the number of bits used to represent each input pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.