From multi-clocked synchronous processes to latency-insensitive modules
From multi-clocked synchronous processes to latency-insensitive modules
复制标题
从多时钟同步进程到延迟不敏感模块
DOI：
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发表时间：
2005
期刊：
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通讯作者：
B. Caillaud
中科院分区：
文献类型：
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作者：
J. Talpin;D. Potop;J. Ouy;B. Caillaud
我们考虑的问题，合成正确的建设全球异步，本地同步（GALS）实现模块化同步规范。这涉及异步包装器的合成，异步包装器驱动模块的同步时钟并以某种方式执行输入阅读，以便在某种意义上保持系统的全局属性。我们的方法是基于弱内隐系统的理论，它给出了标准，保证简单而有效的异步包装器的存在。我们专注于转换（通过添加信令）的同步模块的多锁同步规范弱endo-modules，简单而有效的包装器存在。
We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This involves the synthesis of asynchronous wrappers that drive the synchronous clocks of the modules and perform input reading in such a fashion as to preserve, in a certain sense, the global properties of the system. Our approach is based on the theory of weakly endochronous systems, which gives criteria guaranteeing the existence of simple and efficient asynchronous wrappers. We focus on the transformation (by means of added signalling) of the synchronous modules of a multiclock synchronous specification into weakly endochronous modules, for which simple and efficient wrappers exist.