Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology
Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology
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未来混合 III-V 和基于 Ge 的 CMOS 技术的器件和电路性能
DOI：
10.1109/ted.2016.2603188
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发表时间：
2016
影响因子：
3.1
通讯作者：
Benbakhti B
中科院分区：
文献类型：
--
作者：
Benbakhti B
采用系综蒙特卡罗模拟、漂移扩散模拟、紧凑建模和TCAD混合模式电路模拟相结合的多尺度方法，研究了基于无注入量子阱(QW)结构的20 nm栅长InGaAsGe混合CMOS的器件和电路性能。我们发现，用于混合CMOS的量子阱和掺杂衬底，通过增强载流子限制，有助于降低短沟效应。QW还减少了III-V材料中低密度态的破坏性影响。此外，由于重掺杂的过度生长的源漏接触，计算出的访问电阻比Si中的对应的要低得多。我们预测，与Si-CMOS相比，总体栅极电容较小，驱动电流较大，从而显著减少了电路传播时间延迟(~5.5 ps)。
The device and circuit performance of a 20-nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduce shortchannel effects by enhancing carrier confinement. The QW also reduces the destructive impact of a low density of states in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay (~5.5 ps).