Structural Checking: Detecting Malicious Logic Without a Golden Reference

Structural Checking: Detecting Malicious Logic Without a Golden Reference
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结构检查:在没有黄金参考的情况下检测恶意逻辑

DOI:
10.1166/jcies.2012.1029
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发表时间:
2012
期刊:
2010 17th IEEE International Conference on Electronics, Circuits and Systems
影响因子:
--
通讯作者:
J. Di
J. Di
中科院分区:
--
文献类型:
--
作者:
Jordan R. Yust;Michael Hinds;J. Di

文献摘要

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Many techniques have been developed in detecting malicious logic within a circuit, most of which operate at later stages in the design process. In the Structural Checking method presented in this paper, a circuit design is analyzed at the RTL level to detect the presence of malicious logic. Structural Checking evaluates the overall integrity of the circuit's structure as opposed to its functionality. The design is first replicated in memory through a series of data extraction techniques for preserving its interconnection network, which is then filtered with user-specified primary I/O signal assets such that all internal nets are associated with the corresponding assets. The asset patterns along each signal path are then exposed to a series of attack-detection algorithms for validity check. If any signal path appears suspicious, it will be recorded and presented to the user for closer inspection. Thus, malicious logic can be discovered very early in the design process, thereby minimizing its damage. In addition, the process is highly modularized, allowing for easy expansion or upgrade to include more attacks. Structural Checking lays a solid foundation and provides well-desired guidance to other malicious logic detection methods at various levels of abstraction.