A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores
复制标题
用于可重构逻辑核心的可变粒度逻辑单元架构
DOI：
10.1109/fpl.2007.4380714
复制
发表时间：
2007
期刊：
影响因子：
--
通讯作者：
T. Sueyoshi
中科院分区：
文献类型：
--
作者：
Motoki Amagasaki;R. Yamaguchi;Kazunori Matsuyama;M. Iida;T. Sueyoshi
可重构逻辑器件根据其基本逻辑单元结构分为细粒度和粗粒度两类。一般来说，每种架构都有自己的优点，因此，在各种应用中很难在运算速度和实现区域之间取得平衡。本文提出了一种可变粒度逻辑单元（VGLC）结构，它由一个4位的涟漪进位加法器和配置存储位组成，并开发了工艺映射工具。它的关键特性是可变粒度，这是分别实现算术和随机逻辑所需的粗粒度和细粒度类型之间的折衷。结果，在基准电路中，关键路径延迟和配置存储器位数分别减少了49.7%和48.5%。
Reconfigtirable logic devices are classified as the fine-grained or coarse-grained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit; therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this paper, we propose a Variable Grain Logic Cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and also develop technology mapping tool. Its key feature is the variable granularity being a trade-off between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. As a result, critical path delay, and number of configuration memory bits are reduced by 49.7%, and 48.5%, respectively, in the benchmark circuits.