LATCH: A Locality-Aware Taint CHecker
LATCH: A Locality-Aware Taint CHecker
复制标题
LATCH：局部感知污点检查器
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Lei Yu
中科院分区：
文献类型：
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作者：
Daniel Townley;Khaled N. Khasawneh;D. Ponomarev;N. Abu;Lei Yu
我们提出了一种用于优化动态信息流跟踪（DIFT）的通用架构LATCH（位置感知污点检查器的缩写）。LATCH利用DIFT下的信息流表现出强时间局部性的观察，典型的应用程序在有限的计算阶段操作敏感数据。这个属性允许LATCH使用轻量级的、粗粒度的检查监视大量的执行时间，仅在涉及敏感数据的执行期间调用精确的、计算密集型的跟踪逻辑。LATCH在不牺牲DIFT精度的情况下实现了这一策略。我们提出并评估了三种包含LATCH的系统：S-LATCH在单核上加速基于软件的DIFT；P-LATCH用于加速基于多核软件的DIFT， H-LATCH用于降低基于硬件的DIFT的架构复杂性。我们开发了LATCH系统的FPGA原型，证明其优点对功耗和复杂性的影响可以忽略不计，并且对处理器周期时间没有影响。
We present LATCH (short for Locality-Aware Taint CHecker), a generalizable architecture for optimizing dynamic information flow tracking (DIFT). LATCH exploits the observation that information flows under DIFT exhibit strong temporal locality, with typical applications manipulating sensitive data during limited phases of computation. This property allows LATCH to monitor significant spans of execution using lightweight, coarse-grained checks, invoking precise, computationally intensive tracking logic only during periods of execution that involve sensitive data. LATCH implements this policy without sacrificing the accuracy of DIFT. We propose and evaluate three systems incorporating LATCH: S-LATCH to accelerate software-based DIFT on a single core; P-LATCH to accelerate multicore software-based DIFT, and H-LATCH to reduce the architectural complexity of hardware-based DIFT. We developed an FPGA prototype of the LATCH system, demonstrating that its advantages come with negligible impact on power and complexity and no effect on processor cycle time.