Pulse modulation circuit architecture and its application to functional image sensors

Pulse modulation circuit architecture and its application to functional image sensors
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脉冲调制电路架构及其在功能图像传感器中的应用

DOI:
10.1109/iscas.2000.856321
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发表时间:
2000
期刊:
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
影响因子:
--
通讯作者:
T. Morie
T. Morie
中科院分区:
--
文献类型:
--
作者:
A. Iwata;M. Nagata;Noriaki Takeda;M. Homma;T. Morie

文献摘要

被引文献

相似文献

报道了基于脉冲调制信号的模数融合电路结构及其在焦平面并行处理的功能图像传感器中的应用。该架构基于开关电流集成和时域电荷-脉冲转换技术。采用deep-sub /spl μ m CMOS技术,在低电源电压和低功耗下实现了加/减和乘/加等并行模拟计算。提出了一种实用的CMOS图像传感器,实现了并行PWM读出、灰度图像数据的块平均、简单的模式检测以及二值图像数据的x、y投影和重心计算。采用0.8 /spl mu/m的CMOS技术,在6mm /spl times/ 6mm的芯片上制作了56/spl倍/56像素的功能性图像传感器测试芯片。
Analog-digital merged circuit architecture using pulse modulation signals and its application to functional image sensors with parallel focal plane processing are reported. The architecture is based on switched current integration and time domain charge-to-pulse conversion techniques. Parallel analog calculations such as add/sub and multiply/add are realized with low supply voltage and low power dissipation utilizing deep-sub /spl mu/m CMOS technologies. A functional CMOS image sensor which realizes parallel PWM readout, block averaging for gray scale image data, and simple pattern detection, and calculations for x- and y-projections and centers of gravity of binary image data, is proposed. A functional image sensor test chip with 56/spl times/56 pixels was fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology is described.