Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture
Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture
复制标题
自旋电子阈值逻辑阵列 (STLA) - 紧凑、低泄漏、非易失性门阵列架构
DOI：
--
复制
发表时间：
2012
期刊：
影响因子：
--
通讯作者：
S. Vrudhula
中科院分区：
文献类型：
--
作者：
N. Nukala;Niranjan S. Kulkarni;S. Vrudhula
本文描述了一种新颖的，第一次的阈值逻辑门结构，使用传统的MOSFET和STT-MTJ（自旋力矩转移-磁性隧道结）器件。由此产生的单元，称为STL，这是非常紧凑的，可以编程，以实现大量的阈值功能，其中许多将需要一个传统的CMOS逻辑门的多级网络。接下来，我们描述了一种新的阵列架构，由STL单元组成，可以映射到复杂的逻辑网络。由此产生的阵列，称为STLA有几个传统逻辑所不具备的优点。这种类型的逻辑（1）是非易失性的，（2）结构上规则并且像DRAM一样操作，（3）是完全可观察和可控制的，（4）具有零待机功率。通过实现一个16位超前进位加法器，并与两个优化的传统FPGA实现（超前进位加法器和涟漪进位加法器）进行比较，证明了这些优点。STLA的晶体管数量减少了12倍（与CLA-FPGA相比），减少了10倍（与RCA-FPGA相比），并且随着STT-MTJ器件技术的成熟，其能量将继续减少。
This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Torque Transfer-Magnetic Tunnelling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated by implementing a 16-bit carry look-ahead adder and compared with two optimized conventional FPGA implementations (Carry Look Ahead Adder and Ripple Carry Adder). The STLA has 12X lower transistor count (compared to CLA-FPGA) and 10X reduction (compared to RCA-FPGA) with comparable energy which will continue to reduce as the STT-MTJ device technology matures.