4H-SiC Lateral RESURF MOSFET with a Buried Channel Structure
4H-SiC Lateral RESURF MOSFET with a Buried Channel Structure
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具有埋沟道结构的 4H-SiC 横向 RESURF MOSFET
DOI：
10.4028/www.scientific.net/msf.433-436.753
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
K. Fukuda
中科院分区：
文献类型：
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作者：
Seiji Suzuki;S. Harada;T. Yatsuo;R. Kosugi;J. Senzaki;K. Fukuda
本文研究了具有埋沟结构的4 H-SiC横向R ESU F MOSFET的静态特性。MOSFET沟道迁移率高达80- 90 cm/Vs，沟道电阻低。RESURF ® T的导通电阻为71 m Ωcm，击穿电压为730 V。该器件的品质因数（Vbd /罗恩）计算为7.5MW/cm。SiC功率MOSFET是一种很有前途的大功率电子开关器件。使用SiC的垂直MOSFET被广泛研究为隔离器件[1-3]。另一方面，横向功率MOSFET在功率集成电路应用中起着重要的作用。SiC RESURF（降低表面场）MOSFET已由几个小组证明[4-6]。然而，由于SiC功率MOSFET的沟道迁移率低，沟道电阻高是一个严重的问题。以前，我们已经报道了使用埋沟道结构的4 H-SiC MOSFET的高沟道迁移率[7，8]。本文研究了具有埋沟结构的4 H-SiC横向RESURF MOSFET的静态特性。器件设计和制造本研究中制造的横向RESURF MOSFET的示意性横截面如图1所示。在圆形几何结构的器件中，我们采用了RESURF、栅场板和埋沟结构。Materials Science Forum Online：2003-09-15 ISSN：1662-9752，Vols. 433-436，pp 753-756 doi：10.4028/www.scientific.net/MSF.433-436.753 © 2003 Trans Tech Publications Ltd，Switzerland版权所有。未经Trans Tech Publications Ltd（www.scientific.net）的书面许可，不得以任何形式或任何方式复制或传播本文的任何内容。（Semanticscholar.org-12/03/20，10：57：01）对MOSFET设计进行了二维（2-D）模拟。击穿电压和最大电场的场氧化物氧化物与RESURF区域的掺杂浓度的关系如图2所示。沟道和RESURF长度分别为5和20 μm。考虑到最大Eox，RESURF区域的最佳剂量为6- 7 × 10 - 3cm。MOSFET的击穿电压设计为800- 1000 V。最大Eox随着RESURF层的长度而减小。最大Eox低于3- 4 MV/cm时，需要20μm的RESURF长度。在具有p型同质外延层（来自CREE Research Inc.）的p 4 H-SiC衬底上制造器件。外延层厚度为15μm，有效掺杂浓度（NA-ND）为5.0 × 10 ~（-4）/cm ~ 2。在500°C下通过磷离子注入形成源极区和漏极区。采用多种注入能量和注入剂量，制备了约1 × 10 ~（-1）cm的盒形结构，结深为0.3 μm。RESURF和掩埋沟道区在室温下注入氮。表1总结了每个区域的总se和植入深度。RESURF层的长度为20 μm。在执行所有离子注入工艺之后，在Ar中在1500°C下对注入的杂质进行活化分析5分钟。用LPCVD法淀积了1 μm厚的场氧化层。在湿法刻蚀开沟道区后，用LPCVD法淀积栅氧化层，并在1200°C干O2中氧化140 min，然后在950°C湿O2中氧化180 min，以提高氧化膜的致密性和MOS界面质量。最终栅氧化层厚度为0.15 μm。铝（Al）用作栅极金属和源极和漏极的接触金属。通过在场氧化层上延伸栅电极来制造栅场板。最后，晶片表面用聚酰亚胺膜钝化。表1离子迁移的条件140
This paper presents the static characteristics of 4H-SiC lateral R ESU F MOSFET with a buried channel structure. The MOSFET channel mobility was obtained to be as high as 80-90cm/Vs, resulting in the low channel resistance. The RESURF MOSFE T exhibited an on-resistance of 71m Ωcm and a breakdown voltage of 730V. A figure-of-merit ( Vbd / Ron) of this device was calculated to be 7.5MW/cm . Introduction SiC power MOSFET is a promising switching device for high-power el ctronics. Vertical MOSFETs using SiC are extensively investigated as iscrete devices [1-3]. On the other hand, lateral power MOSFET plays an important role in power IC a pplications. SiC RESURF (REduced SURface Field) MOSFETs have been demonstrated by several groups [4-6]. However, high channel resistance because of the poor channel mobility is a se rious problem for the low on-resistance of the SiC power MOSFET. Previously, we have repor ted the high channel mobility in 4H-SiC MOSFETs using the buried channel structure [7, 8]. In this paper, we present the static characteristics of 4H-SiC lateral RESURF MOSFET with a buried channe l structure. Device Design and Fabrication A schematic cross section of a lateral RESURF MOSFET fa bric ted in this study is shown in Fig.1. We adopted the RESURF, a gate field plate and the buried channe l structures in circular-geometric devices. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 753-756 doi:10.4028/www.scientific.net/MSF.433-436.753 © 2003 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-12/03/20,10:57:01) A two-dimensional (2-D) simulation was carried out for the MOSFET design. The breakdown voltage and the maximum electric field in the field oxide Eox versus doping concentration of the RESURF region are shown in Fig.2. The channel and the RESURF length are 5 and 20 μm, respectively. Taking into account of the maximum Eox, the optimum dose for the RESURF region was 6-7x10 cm. The breakdown voltage of the MOSFET is designed to be 800-1000V. Maximum Eox decreased with the length of the RESURF layer. The RESURF length of 20μm was required for the maximum Eox below 3-4MV/cm. The devices were fabricated on p 4H-SiC substrates with a p-type homo-epitaxial layer (from CREE Research Inc.). The thickness and effective doping density ( NA-ND) of the epitaxial layer was 15μm and 5.0x10 /cm, respectively. Source and drain regions were formed by phosphorous ion implantation at 500°C. By using multiple implant energies and dose s, a box profile of about a 1x10cm and a junction depth of 0.3 μm was fabricated. The RESURF and buried channel region were implanted with nitrogen at room temperature. The tota l d se and the implanted depth of the each region were summarized in Table 1. The length of the RESURF layer was 20 μm. After all the ion implantation process was performed, activation anne ali g for the implanted impurities was performed at 1500°C for 5min in Ar. A field oxide was deposited by LPCVD with a thickness of 1 μm. After the channel area was opened by wet etching, a gate ox id was also deposited by LPCVD and reoxidized in dry O 2 at 1200°C for 140min followed by wet O 2 ambient at 950°C for 180min to densify the oxide film and improve the MO S interface quality. The final gate oxide thickness was 0.15 μm. Aluminum (Al) was used as both the gate metal and the contact metal for the source and drain. The gate field plate w as fabricated by extending the gate electrode on the field-oxide. Finally, the wafer surface wa s passivated with the polyimide film. Table1 Conditions of the ion implantations 140