Compute Caches
Compute Caches
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DOI：
10.1109/hpca.2017.21
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发表时间：
2017-02
期刊：
影响因子：
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通讯作者：
Shaizeen Aga;Supreet Jeloka;Arun K. Subramaniyan;S. Narayanasamy;D. Blaauw;R. Das
中科院分区：
文献类型：
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作者：
Shaizeen Aga;Supreet Jeloka;Arun K. Subramaniyan;S. Narayanasamy;D. Blaauw;R. Das
本文提出了CACHERETERETERETHAT在缓存中的原地计算。在缓存层次结构中的不同级别中，讨论了诸如OperAnd Locality等Compurecaches施加的新约束。还讨论了将问题整合到范围内的简单解决方案，同时保留诸如连贯性，一致性和可靠性等属性。处理，加密内核和内存检查点。微基准表示（54倍吞吐量，9×Dynamicenergy节省）。
This paper presents the Compute Cache architecturethat enables in-place computation in caches. ComputeCaches uses emerging bit-line SRAM circuit technology to repurpose existing cache elements and transforms them into active very large vector computational units. Also, it significantlyreduces the overheads in moving data between different levelsin the cache hierarchy. Solutions to satisfy new constraints imposed by ComputeCaches such as operand locality are discussed. Also discussedare simple solutions to problems in integrating them into aconventional cache hierarchy while preserving properties suchas coherence, consistency, and reliability. Compute Caches increase performance by 1.9× and reduceenergy by 2.4× for a suite of data-centric applications, includingtext and database query processing, cryptographic kernels, and in-memory checkpointing. Applications with larger fractionof Compute Cache operations could benefit even more, asour micro-benchmarks indicate (54× throughput, 9× dynamicenergy savings).