Small chips in crossed wires
Small chips in crossed wires
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DOI：
10.1049/ir:20031106
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发表时间：
2003-12
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影响因子：
--
通讯作者：
C. Edwards
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文献类型：
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作者：
C. Edwards
下一代半导体工艺技术是否会被未解决的技术问题所破坏？随着我们进入2004年，集成电路制造的下一阶段将开始，各公司将开始增加基于90纳米工艺的芯片的生产。但130纳米工艺的糟糕经历，由于制造问题而严重延迟，使芯片制造商变得谨慎。许多公司在看到更乐观的芯片制造商所获得的结果之前，都不愿转向新工艺。一些决定尽早投入的人一直在谨慎地保持他们的选择余地，并在模具尺寸或速度与可制造性之间进行权衡。由于平版印刷技术的快速发展，用于在芯片上制造微小特征的照相工艺，晶体管的缩小速度比20世纪90年代末预期的要快。这些收益尚未反映在其他芯片级功能中。芯片制造商在缩小连接晶体管的导线尺寸方面面临着越来越多的问题。为了在两代之间保持有效的密度加倍，线之间的距离及其横向厚度必须减少约30%。不幸的是，随着电线靠得越来越近，相邻电线上的信号之间的干扰变得越来越难以克服。
Could the next generation in semiconductor process technology be undermined by the legacy of unresolved technical problems? As we enter 2004, the next phase in integrated circuit manufacturing will begin in earnest, with companies starting to ramp up production of chips based on the 90 nm process. But bad experiences with the 130 nm process, which was heavily delayed by manufacturing problems, have made chipmakers cautious. Many companies are holding back from moving to the new process until they see the results that the more optimistic chipmakers get. A number of those who have decided to take the plunge early have been careful to keep their options open and trade off die size or speed against manufacturability. Thanks to rapid advances in lithography-the photographic processes used to create tiny features on chips-transistors have shrunk more quickly than was expected in the late 1990s. These gains have not been reflected in other chip-level features. Chipmakers have faced increasing problems scaling down the wires that join transistors together. To maintain an effective doubling in density between generations, the distance between the wires and their lateral thickness has to reduce by about 30%. Unfortunately as the wires get closer together, interference between signals on adjacent wires becomes harder and harder to overcome.